Hello, this is Dermot O’Bryan from Sparx Systems. In this demonstration we will run over using
the latest SysML options for simulating a digital electronic example in Simulink.
We will use the new SysPhS modelling to reference components defined in Simulink.
For a quick overview of the topics.
We will firstly have a broad look at setting up a digital model for Simulink
Then we will look at using SysPhS Patterns for creating predefined Simulink Blocks.
In this exercise we will use some predefined Simulink components. We will look at how
to model complex Simulink Components in Enterprise Architect using SysPhS
Then we will generate our Simulink model and run a simulation from this
And finally, we look into options for Debugging any issue in the generated Simulink script.
For this example we are modelling a simple binary counter using Flip-Flops, but we will
use it to provide a number of divisions of a Clock frequency. This type of frequency
division was common in - early microprocessor, where you had options for setting fast and
slow clock speeds, for the processor. What we will use is a digital square wave clock,
as an input and see how, in our simulation in Simulink, the frequency output from each
of the flip flops in the series - halves the initial clock frequency.
Before start creating Diagrams and Elements we first of all set our Perspective to SysML.
This opens the Model Wizard. From this we can access some SysPhS Foundation Packages
that we need to reference in the model.
It is best to create a Package to hold both, then select SysPhS, and load the two Libraries
into the Package in the Browser.
Now let's create a Block Definition Diagram.
For the simulation we need to set up a reference to the SysPhS Library.
So, we drag this Library-Package on to the Diagram.
We first set the Package Boundary, on the Block Definition Diagram, to Selectable.
From the Package Toolbox, we can create an 'Import' Connector to reference the SysPhS
Packages.
In terms of Blocks for our model, let's start with the simplest, that is, a SysPhS Block
for a Simulink Constant. We will use it for setting a logical True State.
This can be accessed from the SysPhS Patterns
Under Sources and Sinks, as a Constant.
Now what we want is a Logical Clock to get a digital pulse signal.
We select the SysPhS Toolbox and drag on a Simulink Block.
Then we need to create another Block for our Flip-Flop
What we want is a reference to a Simulink Digital Clock
– so let's get the correct Simulink Path for a digital clock.
This being a Simulink component we find it in the Simulink Library Browser
This can be accessed using Ctrl+L.
You can see this is under the Simulink|Extras|Flip Flops.
We open the Parameters dialog, and work out the path.
In this case it is: Simulink_Extras|Flip Flops| Clock
Then we input that in the Block - in the Simulink Block Name.
The other core component that we need to use
is also pre-defined in Simulink - that is a 'Flip-Flop'.
Again we get the path from Simulink
We place this in the Name field, on the Flip Flop Block, under the heading Simulink Block.
The Simulink Digital Clock has one key parameter, we need to define as a Phs Constant on
the Block - this is: Period (seconds). For this we drag from the SysPhS Toolbox
the Simulink Parameter - we name it 'Period'.
For the Period's Type - which is "Time", we use the
Ctrl+L to set the classifier to "Time" in the SysPhS Library.
For the Time can set this as a Constant to 2, for example 1/2 a hertz. a Period of
2 Seconds, the first second is True - 1, the next second False - Zero.
It also needs an output port. This will need to be a port of type: BooleanOutSignalElement
We can drag this from our Package reference onto the Block.
Then name it as 'y'.
For the Flip flop, in Simulink, it has Ports J, K , Q, QN and a Clock
– so we need to set these up.
Note, these are Simulink components. These differ to the Modelica equivalent in that.
These Ports are NOT identified by a Name, rather they are simply referenced by an Array,
hence the ordering of the creation of these is critical.
The ordering of the Simulink array is from top to bottom for the Inputs
and top to bottom for the Outputs.
For inputs to the J-K Flip-Flop, it is critical, we start with J, then do Clock
Then do K. These are nonetheless shown in alphabetic order on the Block.
We drag on the Input Ports, these are BooleanInSignal, and then name them
to match those ports on the Simulink Component.
Then we do the same for Output Ports using the BooleanOutSignal.
Again this ordered by Q then QN.
In this next section, we will create the main Block that will contain the IBD Diagram
In this new Diagram we connect these Blocks as parts, to form our Flip-Flop Counter.
Now let's create our Block for the Binary Counter.
Then we create a Child Diagram on this Block called Counter. On which, we then drag-on
our Blocks as Components.
For this, it is recommended to use the 'All' option in the Paste dialog.
To display these in the Compartments, we delete the Properties.
The first is the Clock Period.
To keep the diagram clear we alter the Diagram Properties to NOT show the Port Classifiers
and the Property Types. This gives a simpler view of just the Port Name.
For our Constant part, this needs to pass a logical 1 or true state to our J and K Ports.
We will set an appropriate name for this.
We will also give our Clock a more meaningful name.
Then we create 4 parts of type Flip-Flop
Lets name these as Flip-Flop 1 to 4.
Now we reorganize the Ports - placing the outgoing Ports on the left.
We then need to set our connectors between the relevant Ports to fit our proposed model:
- The first; is from the Clock Output, to the Clock Port, on first Flip-Flop.
- The subsequent Flip-Flops are connected from the Q, to the preceding Clock in-port.
We then set the J & K ports to True – by connecting these to the BoolTrue Part.
Ok. That completes our IBD setup
Having set this up. Let's now configure our simulation.
We go back to the Block Definition Diagram.
We see that we have the Counter Block populated with the new parts.
For the simulation we start by creating an Artifact of type SysMLSim Configuration.
Double-clicking on this, opens up the Simulation Configuration.
On opening this we firstly: - Select the Package to simulate
Ensure the Simulink Library is referenced.
Set the Parent Block for the SysML Model that we are simulating – in this case it
is the Counter block. We set this as the “SysMLSimModel”.
We now see the list of Properties available to plot.
So we can select which of these we want to use.
Now, we can run the simulation.
The plot in Simulink is complex – so let's simplify this.
In order to open the generated model in Simulink - we access the EA Generated SLX file.
Here we can see the components, we created in the SysML Model, as shown in the Simulink
format, along with the connectivity we set up in our SysML Model.
We can run this and view the Plot and change, what we want to view.
We start with the output of Flip-Flop 1, then select the last output which is q4.
With each Q enabled, we see the simulation of the clock frequency being halved for each
Flip-Flop that it has passed through.
When doing a complex SysML Model there are bound to be issues
with the generation of the plot.
On that note, let's have a look at the debugging and issue-resolution
when generating to Simulink.
Firstly, we will set up an error. We do this by setting a wrong Connector to the Block
not to a Port.
When we re-run the simulation, we can see, an error created in the Code Build.
This is viewed in the System Output. If we go to the SysML Simulation in the System
Output, we see the error it generated.If we double-click on this, it opens the Configuration
at the Port where the issue occurred. In this case we see
the Clock is the part, where the issue is.
An alternative issue checking method, is to open the generated script file directly in Simulink.
Then view the Diagram and check the Connection. Then you can run the simulation
and view it's Error and see that it is a Connector Issue.
Given this feedback we now do a simple correction of the model.
OK, in conclusion. Let's run over, what we have covered in this demonstration.
This included: Setting up a Digital Logical Model for Simulink
by Using SysPhS Patterns for creating predefined
Simulink Blocks Modeling other complex Simulink Components
using SysPhS generating a Simulink Model – then simulating
and viewing this in Simulink running over how to debug an issue and viewing
the generated Model in Simulink.
Although we have focused on using MATLAB's Simulink, please note that a similar scenario
can be replicated using the SysPhS for Modelica.
Hopefully this gives you a good starting point for getting familiar with the integration
and simulation with MATLAB's Simulink. All being part of the new SysML – SysPhS
features, available in the 15.2 release of Enterprise Architect.
For more information on this see Sparxsystems.com/ea152