In a computer, an interrupt request is a hardware signal sent to the processor that temporarily
stops a running program and allows a special program, an interrupt handler, to run instead.
Interrupts are used to handle such events as data receipt from a modem or network, or
a key press or mouse movement.
The interrupt request level is the priority of an interrupt request.
Interrupt lines are often identified by an index with the format of IRQ followed by a
number.
For example, on the Intel 8259 family of PICs there are eight interrupt inputs commonly
referred to as IRQ0 through IRQ7.
In x86 based computer systems that use two of these PICs, the combined set of lines are
referred to as IRQ0 through IRQ15.
Technically these lines are named IR0 through IR7, and the lines on the ISA bus to which
they were historically attached are named IRQ0 through IRQ15
Newer x86 systems integrate an Advanced Programmable Interrupt Controller that conforms to the
Intel APIC Architecture.
These APICs support a programming interface for up to 255 physical hardware IRQ lines
per APIC, with a typical system implementing support for only around 24 total hardware
lines.
Overview When working with personal computer hardware,
installing and removing devices, the system relies on interrupt requests.
There are default settings that are configured in the system BIOS and recognized by the operating
system.
These default settings can be altered by advanced users.
Modern plug and play technology has not only reduced the need for concern for these settings,
but has virtually eliminated manual configuration.
x86 IRQs See Intel 8259 for a common list and discussion
of hardware IRQ lines in x86 systems.
Typically, on systems using the Intel 8259, 16 IRQs are used.
IRQs 0 to 7 are managed by one Intel 8259 PIC, and IRQs 8 to 15 by a second Intel 8259
PIC.
The first PIC, the master, is the only one that directly signals the CPU.
The second PIC, the slave, instead signals to the master on its IRQ 2 line, and the master
passes the signal on to the CPU.
There are therefore only 15 interrupt request lines available for hardware.
On newer systems using the Intel APIC Architecture, typically there are 24 IRQs available, and
the extra 8 IRQs are used to route PCI interrupts, avoiding conflict between dynamically configured
PCI interrupts and statically configured ISA interrupts.
On early APIC systems with only 16 IRQs or with only Intel 8259 interrupt controllers,
PCI interrupt lines were routed to the 16 IRQs using a PIR integrated into the southbridge.
The easiest way of viewing this information on Microsoft Windows is to use Device Manager
or System Information.
On Linux, IRQ mappings can be viewed by executing cat interrupts or procinfo programs.
Slave PIC IRQ 8 — real-time clock
IRQ 9 — Advanced Configuration and Power Interface system control interrupt on Intel
chipsets.
Other chipset manufacturers might use another interrupt for this purpose.
— any devices configured to use IRQ 2 will actually be using IRQ 9
IRQ 10 — The Interrupt is left open for the use of peripherals.
open interrupt / available or SCSI or NIC;
IRQ 11 — The Interrupt is left open for the use of peripherals.
open interrupt / available or SCSI or NIC;
IRQ 12 — mouse on PS/2 connector; IRQ 13 — CPU co-processor or integrated
floating point unit or inter-processor interrupt;
IRQ 14 — primary ATA channel; IRQ 15 — secondary ATA channel;
ATA interface usually serves hard disks and CD drives.
Conflicts In IBM-compatible personal computers, an IRQ
conflict is a once common hardware error, received when two devices were trying to use
the same interrupt request to signal an interrupt to the Programmable Interrupt Controller.
The PIC expects interrupt requests from only one device per line, thus more than one device
sending IRQ signals along the same line will generally cause an IRQ conflict that can freeze
a computer.
In some rare conditions, two devices can share the same IRQ as long as they are not used
simultaneously.
If one adds a modem expansion card to a system, and assign it to IRQ4, which is traditionally
assigned to the serial port 1, it will likely cause an IRQ conflict.
See also
Advanced Programmable Interrupt Controller Programmable Interrupt Controller
Intel 8259 Interrupt handler
Input/Output Base Address Plug and play
Polling Interrupt
References ^ Oshins, Jake.
"RE: ACPI Machines and IRQ 9 [was: Communicating with the NT developers]".
Retrieved April 17, 2014.
Gilluwe, Frank van.
The Undocumented PC, Second Edition, Addison-Wesley Developers Press, 1997.
ISBN 0-201-47950-8 Shanley, Tom.
ISA System Architecture, Third Edition, Addison-Wesley Publishing Company, 1995.
ISBN 0-201-40996-8 Solari, Edward.
PCI & PCI-X Hardware and Software Architecture & Design, Sixth Edition, Research Tech Inc.,
2004.
ISBN 0-9760865-0-6 IRQ interrupt request
Expansion Bus Configuration External links
More information on the Intel 8259 PIC and its IRQ lines can be found in the IA-32 Intel
Architecture Software Developer’s Manual, Volume 3A: System Programming Guide, Part
1, freely available on the Intel website.
Ralf Brown's Interrupt List