In DRAM, we also have a transistor that is activated by the wordline and
that connects the cell to the bit line.
But we said that's the only transistor we have.
The cell is made out of a simple capacitor here.
So, the idea is that to write to this cell we will activate the wordline,
we put let's say A1 into the bitline.
This transistor connects the capacitor to the bitline.
Now what happens is R1 effectively charges this capacitor.
Once we deactivate the wordline,
the capacitor retains the value that corresponds to a 1.
If we want to write a 0, we activate the wordline.
The capacitor is now connected to the bitline that is connected
to a zero voltage, and we empty this capacitor into the bitline,
thus now our capacitor becomes a zero value.
Now when we disconnect the wordline, the capacitor has nothing in it, so
it retains the value of 0.
So as you can see, the bit is really stored in this capacitor.
When it's charged, we are storing a 1.
When it's not charged, we are storing a 0.
So what's the problem here?
Well the problem is that this transistor is not a perfect switch.
It's a little bit leaky.
Here it's not a problem because if it's a little bit leaky,
these two are strong enough to retain the voltage at let's say 1 and
0 or 0 and 1, while these are not trying to defeat them.
But here our capacitor is slowly leaking into the bit line and
eventually gets empty.
So one problem with DRAM is that it will lose this bit over time, and
that means that periodically we have to actually read out this bit,
figure out what it was, and write it back in at full voltage so
that it can again leak for a while before it gets lost.
Another problem with DRAM that you don't have with SRAM is that
once we open the wordline, the capacitor drains into the bit line.
We can sense what the value was, but the capacitor is no longer fully charged.
This is called destructive read.
When you read a DRAM cell, you have to write it back in.
It loses the value as it gets read.
So this is what is usually called a 6T cell or 6 transistor cell.
That are two transistors that are there for connecting to the cell and
there are four transistors in the cell itself because each of the inverters has
two transistors.
This is, of course, a 1T cell.
Now, the area occupied by an SRAM cell obviously is the area occupied
by about six transistors.
The area of the DRAM cell it looks like it's the area of one transistor and
the area of the capacitor.
The bigger this capacitor the longer it can retain something that corresponds
to a 1 or a 0 before it gets lost, so we want this capacitor to be big.
A capacitor can be viewed as two metal plates placed very close to each other.
The bigger the area of the plates, the bigger the capacitance of the capacitor,
it can keep more charge.
So it looks like, to make a good DRAM cell, we will have to make a big cell
because this capacitor will need a lot of metal area to build large plates,
but this is not how we build this capacitor.
The transistor and the capacitor itself are actually built
as a single transistor in a technology that is called trench cell.
So this end of this transistor is simply buried deeply
into the silicon substrate when we manufacture transistors.
So really the capacitor is kind of buried under the transistor.
So we really get the area of the transistor itself and
not much around it.
You can see also that the DRAM cell
can be smaller because it doesn't need this second bit line.
We just need one, so that also makes it slightly smaller.
We don't need as much wiring there.