Hello and welcome back. If you follow the channel, you already know that my HP 9825,
famously used by Mr. Fancy Pants in the HP catalog,
recently died from a power supply failure that caused an over-voltage.
In the previous episodes, we found ourselves in an Apollo 13 -like disaster,
where pretty much everything in our ship is broken.
Our ROM is bad, our RAM is bad, and our complicated Keyboard Display is bad.
But fortunately, we were able to determine that our rare 16 bit processor is good, so there is
hope. We are slowly turning things around: we repaired the power supply with a transistor swap.
We then focused on the ROM and thanks to our logic analyzer, identified 3 bad TTL ICs, removed a bad
ROM chip, and recovered a missing bit. Finally, as of our last episode, the processor is reading
the ROM and trying to boot. But it does not succeed. Everything points to a RAM problem.
So we're now in a configuration where we can read ROM on our card. This is the original one,
this is the one that's bad. But we can read the ROM now. It goes through the
boot sequence correctly, provided we have the good keyboard from the other machine.
So it starts correctly at address 40, and at this point it jumps to the first subroutine and before
it branches it stores the return address. So it stores 10101 in this location of memory 77633.
Everything goes fine, and that's the return instruction. It's going to fetch the location
that it came from - and surprise! It's not the number we had put there. We had put 10101 and
now it's 10077. I think it's a memory error. What it reads back from memory is wrong by a few bits.
It's partially reads RAM, because it does the whole boot sequence until
it gets into the main loop. And then it reads the wrong result from a RAM chip,
after having checked the whole RAM. So my [guess] - I don't know what your guess is Carl - but
mine is that it's a refresh problem: it loses memory. When it's two accesses very quick [near]
to each other, it works. Unfortunately, the memory - do you have the the memory diagram?
So this whole thing here, all this, all this, all this, all this, that's for memory refresh. So
there [are] many gates that could go wrong. So this is going to be complicated.
To understand this episode, we must first explain how DRAM came to be
and how it works. So here comes the dreaded elevator music.
So in order to understand our memory problem, it's good to understand the history of RAM,
particularly the history of Intel. And here I have a few of the very early Intel chips that tell the
story. This is actually product number one of Intel, released in 1969, and this is an Intel
3101. It is a memory chip that holds 64 bits. No, not 64 kilobits or kilobytes or megabits or
megabytes. 64 bits, that's it. That chip, believe it or not, was quite successful actually, because
it was much faster than any of its competitors. In fact 4 of these fast chips are used in my HP
1607 logic analyzer. They are the ones that store all the ones and zeros you can see on the screen.
Every bunch of four lines is stored in just one of these chips. And by the way it would have been
released in this golden ceramic packages, but I don't have any of the early ones. This is a
successor, this is a 256 bit [chip]. But the one that really made the company is the intel 1103,
released just a year later in 1970. And that one was one kilobits of memory. I actually don't
have any 1103, so I'm using another 1K chip as a stand in, I'll put a picture of the real one. And
there was a huge technological difference between those two: this one is standard bipolar like TTL,
and uses flip flops for the memory element. This one is actually the first silicon gate MOS chip,
and also one of the first dynamic memories. Which means it's far smaller, far cheaper, and
uses far less power than this. And this is really the chip that put Intel on the map
and made a whole company. And of course the significance of this is obvious,
right? This is one kilobit of core memory and this is one kilobit of semiconductor memory.
Now when it came out it [had] a host of problems: price, reliability, the fact that
you need to refresh it - we'll come to that in a minute. But once those were solved, and once
Moore's law kicked in - so the MOS transistor is the one that gave us Moore's law - and you all
know what happened: the core memory disappeared within a few years. Not instantly, it took five
to ten years to get completely rid of it. But of course, today you know we have gigabytes of that
stuff. We have actually made more memory bits than there are stars in the galaxy.
To demonstrate how memory works with MOS circuits, I'm going to actually make a one
bit memory with one MOS transistor, which I'm going to connect through a resistor to a LED, so
we we can tell if the bit is on or off. And it's a memory circuit that I made by accident when I was
trying to develop a light for R2-D2 - I still sell those. But you'll see how simple that is.
So here we go, here's my single transistor memory demonstration:
MOS transistor, LED, input wire connected to the gate. And what's going to happen, is that we are
going to charge the parasitic capacitance of the MOS transistor, and it's going to turn the gate on
or off, and keep it there. So if I do this, it's a one. I just connected it to the plus. If i do this
it's a zero. So a single MOS transistor, just on its own, wants to be a memory.
And that's how your memory is done to this day in your computer, [how] your dram is done. Now
the problem with it, is that when the transistor is much smaller - its minuscule, right, to make
your megabyte memory or your gigabyte memory - the parasitic capacitance turns very, very small,
and the leakage turns up. It is not as perfect as this. So it has a tendency to discharge. And
in order to demonstrate that with that big transistor, I have to simulate some leakage.
So here's the highest resistor I have in my collection. It's a 10 meg, and actually it's not
high enough: it turns instantly off. Which tells you how good the transistor is and how small the
parasitic capacitance is. So I'll add a little bit of parasitic capacitance to make it last longer.
There you go. So I am simulating a more realistic case of what's inside your memory:
that it works for a while and then eventually it leaks out. So that's what's called a dynamic RAM.
It stays for a while. If you want it to stay for a long time, you have to periodically refresh
it. Which means read the bit, and if it's a plus, you reactivate it. And you do that,
in my case here every second, in a real circuit it would be about every few milliseconds.
And that's what's happening in your computer. And I think this is what's not happening correctly
in our memory, is that the refresh is not going on. It has memory for a little while
and then after that it loses it and it causes a memory error. So what is used in the 9825
is actually a later chip. It's a very popular one, the MOSTEK 4116 which was the first 16 kilobit
memory chip. So I have a few examples here, not from MOSTEK. One from Mitsubishi and one from TI.
Sorry folks, but I need to restart the elevator music, because a bare dynamic RAM memory chip
like the 4116 is not as easy to use as you might think. As you can see, this is a 16K by 1 bit
chip, meaning you get only one bit per address from a single chip. You need to use a whole bunch
in parallel, in our case 16, to make for all the bits at a single memory address location.
You can see that from the pinout actually. There is only one pin for the data in
and one for data out, accessing our single bit out of 16k, as advertised.
But wait. To address 16K, you need 14 bits of address. However, if you look at the pinout,
there are only 7 address bits. What gives? Where are the other seven?
This is because, although externally it’s 16K by 1, internally the memory bits are arranged
completely differently, in an array of 128 by 128. You can see this in the die picture.
So to read one bit, you first specify a row address, which will readout a line of 128 bits
in the register that you can see bisecting the array, in the middle. Then you specify
a column address, which will extract one bit out of the 128 and move it to the outside pin.
The other 127 bits are not read to the outside, but however they are used inside for the refresh.
In other words, the process of accessing a row refreshes the entire 128 bits on that row.
So now you get it, for accessing 128 rows or 128 columns you need only 7 address bits.
You use two other lines, Row Access Select and Column Address Select,
to tell the chip whether the current seven address bits are meant to be a row or a column address.
tThis leads to quite a complicated dance to read or write a bit out of the chip.
You have to first present the row address, toggle the RAS line, then present the column
address and toggle the CAS line, at which point you finally get your bit.
And every now and then, you have to do a refresh, which will consist of only a row access,
incrementing the row address every time to scan the whole memory. And also make sure
that does not interfere with the processor trying to read memory at the same time.
A memory controller in the processor and another one in the memory itself will do that for you
in a modern computer. But there is no such help here. You’ve got to do that all by hand,
I mean by TTL. And that’s how you end up with a massive amount of logic to support
the RAM timing and refresh, which takes much more space on the board than the RAM itself.
And sure enough, it’s likely broken somewhere on our board.
It's either something in the devilish logic here or something could happen with our little memory
controller which is actually very very dumb controller. Is' just a three-way multiplexer.
We have instrumented the RAM refresh. Tell us what we're looking at. [Carl] So we have four
signals. The first signal is going to be time, time for refresh. [Marc] And it's the yellow at
the bottom. [Carl] Right, then the next two we're going to look at, the next one up is
the refresh. So that's the signal to the Intel chip to take its internal address for the next
column to refresh, and pass it to the RAM chip so the ram chips will do a refresh
cycle. [Marc] Right. [Carl] Then the third signal we're going to look at is counter
increment. And counter increment is a pulse by the state machine to tell the Intel chip to
add one, so that it moves to the next column. So the next time around it'll refresh
the next column of the chip. [Marc] Right, so refresh is pretty simple, right, it just goes
once every millisecond, reads a column, and a different one every time, right? [Carl] Right,
exactly. And then the last thing that we're going to look at is memory busy, which is the signal
going back to the processor, saying we're in the middle of touching or doing a memory cycle. So we
want to see if it does appear refresh is working. [Marc] Right. And MEB (MEmory Busy), it's my own
interpretation of it after reading the patent, so I might be wrong on it, because it didn't
quite look that way. But this is a good board, so we should see plenty of wiggling action.
Ready? One, two, three... Well, I don't see much wiggling action.
And it did not boot.
[Carl] So what have we tied down? [Marc] Um, I might have the ground bad? Yes, all right,
so I held pin 1 down so it could never count. Okay, try number two. All right. Oh, okay,
it took a while. So single [shot acquisition mode]. So that's a good picture. We should take
a picture of that. So we have time every, every 15 [micro]seconds. We know what the refresh time is.
Then the next one was refresh. [Carl] Yeah, that's pulsing a lot! So it must be going
through... [Marc] Well but it doesn't increment often. [Carl] Right! [Marc] That's interesting.
So it looks like it does multiple refreshes of the same column. But that's what a cycle does,
the refresh cycle on the good board. Well we can we can swap the bad board and see what happens,
right? If you see something very different? [Carl] Yeah, because that's kind of way over here...
Trying to repeat the same experiment with the board from which we think
the RAM is not working properly. Oh, that's completely different!
Definitely that's very different. Well the timing - isn't the timing the other way around?
The timing is timing is... [Carl] Oh look! The count is backwards too! [Marc]
This one looks very... [Carl] Yeah, count is backwards. It should be high mostly. [Marc] Yeah,
so the count is not working. Okay, well, we definitely have a refresh problem. Woohoo!
Okay. Now we have to find out what it is.
So we have been aching over the noodle logic, to find out
evidence that our refresh is not going correctly. And it's pretty hard. It has
gates strung together with no explanation. So at first glance, it looked like the
signals from the good board and the faulty board were very different.
There was one piece of good news though, the timing signal for the beginning of the refresh,
the yellow trace at the bottom, worked on both. So clearly it was at least trying to refresh.
Confident that there was probably some big bad logic fault, we started a simple
blind debugging approach, checking every individual logic gate in the noodle logic.
But every single one seemed to work properly!
Moreover, the processor was not booting properly with the faulty board, and thus was not accessing
RAM in the same way at all. So making comparisons with the good board was almost impossible.
Clearly, the blind debugging or the compare approach would not be good enough.
So, debugging the RAM control circuitry is turning out to be quite a challenge. First,
there's a lot of it, right? You see the RAM here, and the ROM, and pretty much everything else is
this control logic here. So there's a lot of it. It's quite un-obvious what it does, and every
gate we tested in this mess seemed to work fine. So, in order to understand better what it does,
it seems that we have to gain a much deeper understanding of it, and I decided to simulate it.
And behold, here is the grand refresh logic simulation. Instead of using
classic Verilog simulation, I chanced upon this software called Logisim Evolution.
Oh and by the way, when it beeps, it means there is a refresh cycle in process.
And that turned out to be the perfect tool for what I wanted to do,
and I have to say that for a free tool, originally made for teaching logic design,
it is quite amazing, even if a little buggy. But as you can tell, this is quite complicated,
and it’s getting quite late in this episode. We’ll get to play with this logic simulation tool,
deep dive in the crazy gate logic, and see how it pointed us in a completely
different debugging direction, when I hopefully see you in the next episode.