In 2021, TSMC fabbed about 12 to 13 million 300-millimeter wafers.
Assuming each die is about 100 square millimeters large,
that is about 8 billion chips. Eight billion.
Semiconductor manufacturing is the most sophisticated, unforgiving high volume
production technology that has ever been done successfully. You need a lot of practice.
The more chips that TSMC makes, the better it gets at it.
In this video, I want to talk about how a fab like TSMC improves their operations.
How they think about yield, speed up throughput, and in general get better at wafer fabrication.
Wafer manufacturing is hard. To break it down, there are mask layers - where a mask is used
to reproduce a pattern onto a substrate. Each mask layer requires about 15-25 process steps.
These steps include oxidation, photolithography, etching, ion implantation, washing and so on.
A simple 180 nanometer process chip, which was leading edge some 20 years ago,
has about 20 mask layers. That means a single wafer can take up to 600 steps.
Remember, this is a chip from like 20 years ago.
Today's leading edge processes - which TSMC calls N14,
N16, and N10 - can have up to 60, 70, 80 mask layers.
You can't pass bad wafers to your customers. Bad dies that cannot be repurposed somehow
have to be thrown away - with its cost distributed amongst the good dies. If your yield is 50%,
then the impact is that the cost per good unit is twice as high as it possibly can be.
Broadly speaking, yield is defined as the fraction of total input
transformed into a shippable output. But that is composed of several components.
For instance, line yield is the fraction of wafers that make it to the final wafer electrical test.
Die yield is the fraction of dies on good
wafers that make it through to the assembly and final testing stage.
And final test yield is what makes it through that assembly and final testing stage.
Independent fabs have the most direct control over the first two - line and die yield.
Maintaining good final yields across some 500-600 steps is super hard. Defects need
to be tested and detected as fast as possible so that technicians can
quickly respond to them and fix the line before more wafers have to be scrapped.
On a process with 400 steps - even if each step has an average individual yield of
98% - the die yield of your wafer will be just 0.03%. Which means 3 good dies out of 10,000.
You need 95%. One TSMC customer - a Chinese company called Canaan, says that their
yields - using TSMC's 16 nanometer process node - were about 95-96% over the past few years.
TSMC 16nm has some 60 wafer layers, which means about 800-1200 steps. So imagine doing something
that has to succeed 99 point whatever percent of the time 800 to 1,200 times at high speed.
It gives you a sense of the challenge these fabs are grappling with.
So what causes yields to decline? It's a billion dollar question!
The reality is that almost anything can affect yields in a negative way.
Here, I will go through just a few of my favorites.
There is the concept of killer particles. These are anything large enough to cause
defects in semiconductor production in the same way dust on a negative causes a visual defect.
They can come from anywhere. Defects in the starting materials
or ultra-pure water for instance. Certain processes like sputtering and plasma etch
can generate killer particles too, impacting the overall yield.
As process nodes and feature sizes advance, the bar for what defines a killer particle
ratchets lower. Recent discussions in the ultra-pure water industry are implying a
killer particle size under 10 nanometers, which is roughly the diameter of DNA.
These particles can attract static charges, causing additional direct damage to the wafer.
These electrostatic discharges are just 1-10 nanoseconds long, but can cause melting damage.
If these static charges reach and damage the mask - which as I mentioned contains the chip design
pattern - then every silicon wafer produced thereafter is damaged too. A very big deal.
Lastly to close, my absolute favorite yield flaw - stochastic effects in EUV lithography.
EUV has made possible feature sizes so small that foundries have to
start considering the probabilistic nature of atomic scale interactions.
At this scale, there is only a probability that a photon will be absorbed at a certain location.
Microbridges - lines where spaces should be - and broken lines - spaces where lines
should be - are common printing errors largely due to randomness.
These have been observed before, particularly in immersion lithography.
But were not a major concern back when the feature sizes were larger.
No longer the case when talking about sub-10 nanometer process nodes.
Modern foundries use computational lithography techniques to compensate
and print better features. This software has to now account for these probabilistic interactions.
For instance, older versions were programmed to assume
discrete edges. Now they have to be reprogrammed to replace those edges with gradual approximations
on a continuum. Very cool stuff that I should do a video about in the future.
No foundry starts off a new process node at 95%.
They have to get there through a process called "yield learning". This is where
the foundry goes through and eliminates individual sources of faults one by one.
If you were to plot time against yield, you get a basic curve.
This is how you want it to ideally go. At the start your yields are at about
20-50%. You struggle to figure out what is going on for a while, until you figure it
out. Then you rapidly get to an acceptably high number which plateaus thereafter.
The time it takes to get to that high plateau number is called the "time-to-yield". The shorter
it is, the better. And this speed is directly correlated to foundry profitability. Here is why.
The price of a product gradually decreases after it is released to the market.
So if you can ramp up the yield faster than the price of the product declines,
that is when you earn the highest profits.
Per an older research paper, TSMC seeks to speed up its learning rate for advanced nodes about 18%
a year, and their mature nodes by 4-12%.
As semiconductors have gotten more complicated, the process of yield learning has gotten harder.
Early on most fabs relied on experienced engineers eyeballing the data,
doing experiments and accordingly adjusting the recipes based on the eyeball analysis.
For instance, Motorola Semiconductors once had a situation where wafer yields
on a mature process suddenly degrade by 5 percentage points - a significant
deterioration - for no reason before mysteriously recovering.
These flawed wafers can only be detected in final testing due to the sensitivities required.
It took 5 years and 30 experiments to figure out what was going wrong. Various teams exactly
reproduced the wafer fab line, brought in scanning electron microscopes, and more. It took sheer
luck in a four-factor experiment to discover what eventually led to a faulty emitter pipe.
Yield learning as it is today has become a far more data and automation-heavy effort.
The whole fabrication process generates and collects millions of pieces of data each day.
Finding patterns in this data with its hundreds of
attributes have scaled far beyond traditional statistical methods.
Thus, engineers have been throwing machine learning
models on top of this data to help find new improvements.
For instance, let's take the photolithography process. It has many input parameters that are
measured. Examples might include the time spent dunking the wafer into a specific chemical agent
or how long you spend mixing some other chemical prior to its usage.
This process inevitably results in faults like hot spots and overlays. But the correlation between
them and the inputs are non-linear and difficult to uncover without a more sophisticated tool.
This is where the machine learning model is employed to help refine
the photolithography recipe and achieve optimal results.
Such big data methods would have helped pinpoint the aforementioned Motorola flaw
in a few weeks rather than the 5+ years it took using traditional experiments.
Thus TSMC employs hundreds of IT and AI engineers to run such data analyses.
Furthermore, there is a great deal of physical automation inside the fab. The less the material
is handled by a human person, the less likely killer particles can get into the location.
We get a lot of photographs of people in cleanrooms,
but nowadays people only go inside to do maintenance.
Robots have replaced all the people, largely due to cleanliness and weight issues.
Over the years, wafers have become larger. The current standard wafer is 300 millimeters wide,
roughly a foot. They are stored in things called
a Front Opening Unified Pod, which I will refer to as FOUPs.
Fully loaded to its 25 wafer capacity, a FOUP weighs about 19.8 pounds (9 kilograms). Since
it is physically difficult for an average semiconductor human worker to move
a fully loaded FOUP, fabs have to be configured to have robots do it.
The robot takes the FOUP to a machine bay, usually via an overhead railway system.
The machine opens up the FOUP and processes the wafers inside.
Then it loads up the FOUP and closes it. The robot then takes it to the next machine.
Most of these machines are supplied from - where else? - Japan.
Muratec and Daifuku - which sounds like a mochi but isn't - are the
leaders in machine tool technology and automation for your cleanroom.
Studies have shown that the most successful fabs have the most useful automation systems
inside their clean rooms. Having the flexibility to use robots to
adjust the manufacturing process on the fly is critical in maximizing speed and throughput.
Fabs measure how fast you can work through a single mask layer using a metric called
"cycle time". TSMC is obsessed with it.
I briefly talked about this in a prior video but they care for it more than the actual yield.
This is because simply accelerating the cycle time allows for more "work in progress" turns,
more data, a faster learning rate, and thus faster time-to-yield.
In the late 1990s, TSMC pioneered a dispatching system to maximize
its equipment utilization rate and speed up cycle time. The system considers technical
and business factors to decide which wafers to send to a station and when.
A simple technical example involves a furnace and a wet bench - not a real
bench but an automated tool for wet chemical processing.
The wet bench can batch four FOUPs at once, so when the furnace is about to finish,
it coordinates the robots and wet bench to prepare for arrival.
Trying to figure out the "when" part is challenging.
TSMC uses a remarkable theorem in queuing theory called Little's Law.
It is expressed as N = λ T where N - the long term average inventory level of a queuing
system - is the product of lambda - the arrival rate of the wafers - and T - the cycle time.
The company is able to use a derivation of this formula to calculate the remaining
cycle time and optimize or adjust their automated dispatch times accordingly.
TSMC and its customers are in a race to deliver good product to the market
before the profit window closes. Countless fabless firms make it
clear that their number one requirement isn't price but rather, lead times.
TSMC is able to leverage its customers' huge volume to generate more data and
optimizations than any of its competitors.
Each new customer who joins the roster adds to TSMC's edge in data volume and yield learning,
while simultaneously sharing in its operational benefits. Scale matters.
TSMC discusses their time to yield progress for certain leading edge nodes as part of
their annual Technology Symposiums. The last one we got to see was N5,
and that was looking quite well. Likely generating a great deal of profit for the foundry.
Next up is N3 - dubbed the 3 nanometer process. Based on recent rumors, this one is having some
issues. It is kind of fascinating to think about the countless hundreds of little experiments,
adjustments, and improvements the company is running right now
as fast as it can in order to get to an acceptable plateau.