welcome to the HDL quarter of video series in this video series we will
learn a popular production proven path to take a MATLAB digital signal
processing algorithm through similan fixed point designer and HDL coder to
target an FPGA in previous videos in this series we have discussed the
strength of MATLAB and Simulink created the Similan model of the pulse detection
algorithm introduced design architecture options that xn control over speed and
area trade-offs and converted the Similan design to fix point in part Phi
of the video series we will generate and synthesize the optimized HDL code we
will take the following steps to generate the HDL code first we will
check the model's compatibility for cogeneration and then launch the HDL
workflow advisor to generate the HDL code the pulse detector subsystem or the
device under test dot contains the algorithm for which we will generate the
HDL code we will begin by saving and renaming the model and check for any
incompatibility in the pulse detector subsystem select the check model
compatibility by right-clicking on the DUT under the HDL code option HDL model
checker not only n chose of the blocks used in the subsystem is real compatible
but also ensures the settings ports and configurations of these blocks do not
generate inefficient hardware the HDL model checker includes options for
native floating-point and industry standard checks as these are not
applicable for this example we shall ignore them after the selected checks
are run non-compliance status is displayed as warnings or failures in our
case two warnings are highlighted to navigate to the source of the warning in
Simulink model news a link provided reported warnings are likely to prevent
optimization features to function properly and end up consuming additional
hardware resources to automatically correct the warnings
you can change them using the modify settings a hatch tml report is generated
which shows results on each run of the model checker with a timestamp in the
next step we will utilize the HDL workflow advisor to generate the HDL
code to synthesize the generated VHDL or Verilog code we will use a third-party
tool in our case silence Vivaro HDL coder supports a broad range of
synthesis tools such as Intel micro samee to name a few using the HDL setup
tool path command we will assign the synthesis tool to a MATLAB system path
launch the HDL workflow advisor by right-clicking the DUT and select HDL
workflow advisor from the HDL code option the HDL workflow advisor guides
you through the stages of generating the HDL code for the DUT and the FPGA design
stages using a range of tasks in order to run these tasks we will set each of
the tasks folder options with details of our design and hardware package
information of the synthesis tool target device details and target frequency will
be defined under the set target folder and settings relating to global reset
report generation are done in the HDL code generation section click apply to
save the selected choices and right-click on subfolder 3.2 and put
tasks to initiate generation of HDL code when HDL advisor completes running the
tasks you have successfully generated the HDL code the resulting generated HDL
is well-structured commented and readable and you can navigate from
specific lines of HDL code to the model or MATLAB code the code generation
report lets you review resource utilization estimates such as multiplier
DSB blocks and optimization options such as pipelining resource sharing and delay
balancing furthermore you can view the model changes in the DUT using the
generated model link option and even simulate the generated model to ensure
it works correctly with the optimized timing with the HDL code generated you
can either choose to utilize the workflow advisor to create the FPGA
synthesis else use a synthesis tool of your choice
in this video we will utilize the first option with the logic resources mapped
on the FPGA we can visualize and identify the pre and post routing timing
information and highlight the critical parts in the model this analysis uses
the annotate model which synthesis result option and enables the HDL coder
to display the DUT with more accurate critical path timing with the steps in
the workflow advisor complete you can verify the HDL by utilizing
co-simulation on the workflow advisor with the core simulation option we can
verify the RTL matches the Simulink and matlab behavior with this fifth and
final video on the HDL quarter video series we have successfully generated
and synthesized the optimized HDL code for the pulse detection algorithm
implemented in matlab to learn more on the HDL quarter product visit the math
works website and explore math works getting started page two design explore
generate and verify HDL code generation for FPGA ASIC or system-on-chip
prototype or production projects