Hey guys, I will talk about another important topic in semiconductor packaging which is the package structure.
This will help to have a better understanding of semiconductor packaging and the corresponding assembly processes that I will discuss in detail in future videos.
This is Lito Galera and welcome to my Watch Learn ’N Play channel.
Let’s start with the common wire bonded leaded packages. These are the ones that have the leads extending out on the sides like “gull wing”.
If you have seen before a printed circuit board populated with components, it is very likely that there is at least one component of this type.
These packages are QFP which has leads on all 4 sides, and also SOIC, SSOP, TSSOP type packages which have leads on 2 sides.
Let’s say we cross-section the package, slicing the body of molding compound and through the die.
What you will see in the cross-section is the illustration on the right side of your screen.
There are basically 5 main components in the cross-section of a wire bonded package - die, wire, epoxy, DAP, leads, and molding compound.
To understand the details of package construction, let’s zoom in on the cross-section as shown on the right side of your screen.
Very important requirement of any package is the package thickness. The package thickness is not just a random or preferred thickness by manufacturer.
This is actually defined within the JEP95 JEDEC standard which is the standard document for package outline in microelectronic industry.
The standard package outline drawing details all the important dimensions that manufacturers follow
This is very important so that users can get devices from different manufacturers without worrying about footprint compatibility to their printed circuit board (PCB)
To learn more about JEDEC standards, you can visit their website at www.jedec.org
If you register you can actually access some free standards which are good for learning
Going back to our discussion, package thickness limits the height or vertical space the manufacturer can operate
Note that package thickness is different from package height. Package height is measured from the seating plane height to the top of the package
This dimension is also defined in JEDEC standard
Leadframe thickness is also defined in standard package outline drawing
Most manufacturers use the same leadframe thickness especially if they are getting their leadframes from the same supplier
This is very cost efficient for both manufacturer and suppliers by saving on tooling cost
You will notice that the leadframe has downset, that is the die attach pad is actually lower for gull wing type packages
This gives more vertical space for the die and wire. The green color in the illustration is the die.
Die thickness varies between manufacturers or even devices of the same manufacturer.
In general, it is cheaper and easier to use thicker die. The thicker the die is the less prone it is to breakage and easier to handle than thinner die
Raw wafers are thicker, roughly about 24 mils (or 0.6mm) thick
For standard packages the wafers are thinned to about 10 to 20 mils thick
Advance packages requires much thinner die
Bond line thickness (BLT) is the thickness of adhesive or epoxy between the die and die attach pad (DAP), typically at least 1mil (25.4um).
Loop height of the wire is measured from the die surface to the top of the wire
You will notice that the wire is very close to the top of package
In general, the wire-to-package clearance must be at least 2 mils or 50um
Otherwise there is a risk of wire being exposed after laser marking the package
Let’s talk about Quad Flat No-Lead package, or commonly known as QFN. QFN also uses Cu leadframe, however, the leads are not protruding on the side of the package
Without the protruding leads, the QFN package is actually smaller than typical gull wing packages
This package is very popular for mobile devices or any electronic devices that requires much smaller space
QFN leadframe has no downset, that is the leads and die attach pad are of the same height
It is also a thinner package, typically around 1mm thick, thus it requires a thinner die and leadframe, and low loop height
A significant advantage of a QFN package is the “exposed pad” which helps improve the package thermal performance, particularly for discrete devices
Ball grid array or BGA is for high pin count applications, specifically for high pin count ICs
It uses laminated substrate made of layers of Cu and prepreg. BGA has many different configurations
An example is the typical die attached - wire bonded die configuration. For wire bonded configuration, it requires thin die and low loop height
Another configuration is using flip chip die. It can also be a combination of wire bond and flip chip die in a multi chip application
BGA terminals are array of solder balls, and also of various configurations depending on device requirement
I’ve shown basic structure of common packages. And there are many other packages of different structure, particularly in advanced packaging
However, I will not cover them yet in this video so it won’t be overwhelming
I’ll be uploading more videos, related to wafer saw, die attach, and wire bond with more process details
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