I mean it's a excellent question.
some of them are self-limiting, some of them are not.
So, for example, if you have a larger let's
take a case where you don't have an air gap.
That was going to have some variability in terms of it's loading and coupling because
CDs are different, spaces are different. So you have some variability there.
With an air gap, it can be thought of as self compensating.
So if you have a large space.
You have a large air gap, air gap doesn't fill as well,
so it actually you know, increases via, via, from that point of view.
But their space was large to to begin with, so the relative energy is low.
So, as an integrative picture, the variability is not
any worse than what you would have without an air gap.
The other next thing was ONO oxide nitride oxide.
So, I mentioned a while ago that you needed something
close to 120, 140 angstroms in physical layers, and physical thickness.
So that's good, in a 90nm flash, a 10nm thickness
of ONO on either side, it's not a big deal.
You can tolerate that.
But now scale it down to a 20nm flash, I have 12nm ONO on each side.
I don't have space to put a control gate in addition to an ONO gate.
So essentially I've just run out of space to put that dielectric there.
I cannot not have a wrap, because then that
really, really screws up my gate coupling ratio, and
as a result we're in a very tight box. So there isn't enough space to between the
floating gates to actually accommodate the Poly2 and the ONO at a 20 nanometer node.
and available gate said no.
how can you still maintain your gate coupling ratios but not have a wrap?
So, here this is what I call biowrap, so you have
a floating gate and you are wrapping it around the control gate.
No, go to a plainer set,
where the control gate really is completely plainer.
And in order to maintain the gate coupling in such a scenario, you have
to have something which has much higher
a balance between the constant speed of barriers.
So we thought about putting a
[INAUDIBLE]
electric in this particular one, and that would facilitate
us going to a planer cell in this particular direction.
Uh,the requirements of this high key are very
different than what we usually optimize for logic.
Logic is all about mobility. there is
[UNKNOWN],
I really don't care about mobility, because there
is no mobility happening between poly1 and poly2.
But I do care a lot about leakage, and at this high fields these dielectric.
We don't even look at these dielectrics in the
logic case, because we're talking about 1.8 or lower volts
[UNKNOWN]
but as well I'm still talking about
[INAUDIBLE]
volts. we put this thought into action.
So this is what I think is a biggest change from what technology
graphs we've shown for a while, we have fully planer cell right now in production.
which uses high key and gets away from these
[UNKNOWN]
issues.
So it's it's the first planer cell of it's kind, it's the
first cell which uses high key and flash in the same environment.
And as a result we do have the smallest cell size in the whole industry.
So, we mentioned, we're not the gorillas yes, but technologically we are
leading the pack in terms of innovations as far as the scaling is concerned.
So, it, it is the best solution for 20 nanometers and
we strongly believe that is a scalable solution beyond this also.
so, very proud of this innovation that came out of our group here.
so, talked about a few things air gap and linear high key cell.
what about the other things that I've mentioned.
Few electron effects As
the dimensions scale, the cell capacitance scales.
So you have less number of electrons stored per unit
level So, every electron starts mattering more and more, because
it has very high impact on the Vt, which is
the domain which actually determines what becomes ones and zeros width.
And that's a big problem.
The channel area scales, and with the gate
oxide not scaling, we have less number of electrons
in the channel as well.
So, I talked about less number of electrons in the floating gate.
We also have less number of electrons in the channel.
And again, if you have some interface states where electrons go in and out,
you're going to have a large you're going to have 1 of f, which you always do.
But then the impact of that is going to be very large.
In addition to that you are talking about literally hundreds of
[UNKNOWN]
of area, so random dopant fluctuations also becomes very, very tricky.
just a few very good good work from now, now micron I guess, but SD at that time.
what they are showing is as you the statistical distribution in the
number of injected electrons during programming
actually introduces fluctuations in the cell.
So, I'm trying to go put 100 electrons, when your actually
going to have a variable there from the, because of this number fluctuations.
And this fluctuation, the impact of these fluctuations
increases pretty significantly as the cell size, scales down.
something similar, the channel electron trapping and de-trapping during read
also causes the current to fluctuate, and this is essentially RTS.
So, this is a measurement added 9 years ago.
You can actually start seeing
the impact, and this impact scales pretty seriously
as we go to smaller, and smaller nodes.
There are seconday effects about channeling and all that.
But to the first outer RTS is very big problem.
So, RTS is, Random Telegraph Signal, because it looks like that kind
of a graph, where you have a square going up and down.
what it the reason
RT, you have so, how do I, what is this measurement all about?
I'm measuring a drain current at a fixed voltage
for a long amount of time, and that's this graph.
So x axis is time, y axis is the drain current.
Because of trapping and de-trapping of
the electrons in the interface, you're going to
have different either Vt or mobility or both for the carriers in the channel.
And that affects your drain current.
So that's the reason my current is going up and down as a function of time.
Now if I keep measuring for a long amount
of time, I'm going to scan a whole bunch of traps
at different energy depths, different spatial locations, different trap
constants, different life constants, all that other, the whole variable.
And I'm going to see larger and larger fluctuations as
I measure a sample over larger and larger time.
So that's the sense of RTS.
and now you can see that if I'm conducting housing carriers and I have one trap
or two traps, one electron is not going to have as much impact on the drain current.
But if I'm connecting ten carriers, that
one electron is going to have a significant
amount of impact on your drain current, which is what decrements ones and zeros.
So that's why scaling
makes the impact of RTS much worse.
And not much you can do about it, especially if
you want to have costs scale savings by making things smaller.
So this is just one cell.
If I look at large numbers of cells, that's how I look
at a whole bunch of energy depths, locations, all of that stuff.
And you can actually see the variation just keeps getting very
large.
this, this is an example of a simulation by a Japanese group.
You can see that what, here I'm showing is statistics.
So if a median cell doesn't really have too many
[UNKNOWN],
but if you look at a large number of cells you see that the noise amplitude.
Which is, if I go to the earlier plot, the difference in the min and the max
of this scaling, just keeps getting larger and
larger, and it's pretty proportional to, somehow related to
the area.
There are secondary effects where now if one trapped electron can actually deplete
the entire channel, because your talking about such a small, literally 200, 200
[UNKNOWN].
And that just increase fluctuation, increase
the impact of one electron being trapped.
So, the few electron effects, not much you can do about it, because it's kind
of fundamental. So, we, how do we go forward from here.
So we are at 20, we have a pretty innovative,
[UNKNOWN],
we can keep going for a while.
But, this is where a dramatically new approach comes in.
So beyond planer cell, the non-scaling will continue,
but it will go in the vertical direction.
So it'll look somewhere in the 3D
[INAUDIBLE]
direction.
So instead of trying to make things smaller
and smaller, just stack a whole bunch of things.
So effectively from a cell size area,
you're actually getting a lot of improvements.
instead of planning to make things
smaller, and actually running into physical limits.
a lot of companies are spending a lot of
time and resources looking into these various 3D architectures.
lot of, lot of processing technician details here.
So, I just give you a flavor of what these different companies have.
So, Toshiba is looking at something called pipe BiCS scalable architecture.
Samsung is looking at TCAT.
Various, Various acronyms essentially trying to differentiate
their non-technol, 3D technology from different people.
At the device level or at the very high level, you can classify them in two ways.
Either I'm conducting current in the vertical direction.
Which are the first three approaches from
the Toshiba, Samsung, and, Hynix I believe.
Or I'm conducting in the horizontal direction, which is a micronics
approach, which is very innovative, very different and has its own trade-offs.
So those are two cells, and then there are
lots of variations that people are looking around it in
terms of how many layers can I stack, can I
even etch this thing, what is the aspect ratio needed.
lot of, lot of structure related work
and effort that happens in this particular area.
what it buys you from a device point of view again, is for a effectively
small cell print, the physical cell size of this structure can be pretty large.
So, I'm still going to get all the bit saving,
cost savings as if I'm making a very strong cell,
but that's because I'm amortizing it over a bunch of
layers, which are 16 or whatever else you want to make.
this is the key breakthrough that
will provide a lot of relief to the
scaling issues caused by these few electron effects.
but you can see that this is, technology field that gets
to be fully perfected, and it's going to have its own challenges and
[INAUDIBLE].
It's going to introduce more degradation, and it's going to have its own challenges.
So it, it's going to be challenge.
One thing you'll notice is that tunnel oxide.
in all these structures, one common theme is that
tunnel oxide is usually grown on a poly silicon surface.
And that itself sets you in a very,
very different war regime in terms of liability.
So, 3D will have its challenges.
But that will be the key breakthrough that'll keep the scaling of man going.
so that's pretty much all I had.
so yes, flash memory is playing a very
important role in the way we live and work.
from phones to large CDs and every which way.
This has been enabled through real
continued technology scaling over the past years.
The path ahead is more challenging than what we have come over.
So we are already looking at pretty drastic material
changes, and now we are looking at structure changes.
And it's much more
challenging, and there are a large number of
possible technical paths that we can go ahead.
I think that should answer your question that
we don't know the path, there are many options.
But at a high level with the planar, followed by a 3D
structure, we do see nine scaling going on for several more generations.
So, yes there is a red brick wall, but we
keep pushing it further and further away in terms of
limits.
Flash is, see with power consumption depends on two things.
One thing is the density of the whole die,
and the actual chip that you're, the cell scaling.
With cell scaling actually, power doesn't scale.
What hurts you is because you're going to larger and larger
gauge sizes, so you're trying to program more
and more bytes in the same panel operation.
Those are the things that hurt you.
But scaling facilitates you going to bigger die.
And bigger die is always more, is better because I can put
more memory in your same, relisted that your giving me on your SSD.
So that is the reason why ball's actually non-die
is going up, but nothing to do with the fundamental
cell, is due to the die architecture that you are choosing.
So yes, active power does go up. Especially during programming.
Programming is the limit of our power.
because you are essentially trying to take the entire
word line to 20 volts, which is a lot of
[INAUDIBLE]
that you have to drive.
and it's scaled because of page length and other
effects, not as much but in terms of itself.
Not a question can be answered without lots of graphs.
but I can point you to a few papers
and they walk through the process of a belief step-by-step.
Essentially it's a, let's take this first example.
You're depositing a lot of stacks in one shop, you're breaking
it up.
That becomes your gate, and then your deposit
your active conformity, and that becomes your actual body.
So that's a 30-second reply, but it's oversimplifying to a very large degree.
the first question, five companies are too many?
yes and no.
so we have what Samsung, Toshiba, Micron and Dell, Hynix, and other companies,
which are probably below in the sub 1% kind of maybe sub 5% kind of market cap.
So,
[CROSSTALK]
[INAUDIBLE]
is Toshiba so essentially they are together.
Toshiba is essentially the foundry, it's not,
it's a full GDP but, Toshiba means Toshiba
[UNKNOWN]
yes.
each one of the companies, very big.
Each one of them is very highly vested in this is kind of a cheap storage memory.
And you can see the dam is huge. So the carrot is there.
People are not going to get rid, I mean,
not going to walk away from a 50 billion dam.
so I don't see anybody from these key players really
walking away, because that is their core bread and butter.
So
and everybody plays it to their own strengths.
For example, Intel micron go with innovation.
That's how we keep ahead of other costs. We are in literally in the US.
So costs are higher, but we stay
ahead with innovation in terms of everybody else.
Samsung goes with scale.
You can't beat them with that kind of a thing.
Hynix was this plain simple cause that in minus 2
kind of technology, but they milk it to the point where
the yields are so high that they still make money out of it.
So everybody prays to the
[INAUDIBLE],
so I don't think these big players are going anywhere
because of just the, that's their core bread and butter.
They have the horse power to go off it, and
market is big enough to actually be able to support that.
So don't think yes, lesser would be better for the remaining few, but I
don't think that's really going to happen. The second question was actually
the question that you've posed is exactly the panel discussion topic this December.
Alice Gardner think that I'm defending NAND.
So this is a good practice for me. >>
[INAUDIBLE]
>> Yes I am. >>
[INAUDIBLE]
>> That's IDM this December. Yeah.
so to the first order, I mean.
NAND does so much better that anyone wanting to displace NAND needs to grow.
So there has to be a niche technology which has to really get
foothold, which has to it has to prove itself and then start growing.
So we are, I think we are quite a ways
removed from talking about replacing NAND.
There is a very good chance where there'll be synergy,
where other technology will start working in their own niches.
And if something clicks here, I really need the performance that
this technology offers, or I really need the density that it offers.
Things could take it from there, and then you have
[UNKNOWN]
principle that says, I have this thing, now I'll explode it to its limit.
But in terms of status, there is such a
wide chasm between NAND and the rest of the technologies.
That, it's a long time before somebody
really, really challenges and starts talking about replacing.
I don't think it's a near term thing.
But yes, the other technologies are very exciting.
They each get something unique
to the table.
And they have to find their own niche, get foothold, grow, and then we can talk about
[INAUDIBLE]
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[INAUDIBLE]
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