In computing, DDR4 SDRAM, an abbreviation for double data rate fourth generation synchronous
dynamic random-access memory, is a type of synchronous dynamic random-access memory with
a high bandwidth interface, expected to be released to the market sometime in 2014. It
is one of the latest variants of dynamic random access memory, some of which have been in
use since the early 1970s, and a proposed higher-speed successor to the DDR2 and DDR3
technologies. It is not compatible with any earlier type of random access memory due to
different signaling voltages, physical interface and other factors. It was released to the
public market in Q2 2014 with a focus on ECC memory, and an anticipated launch for non-ECC
modules in Q3 2014.
Benefits The primary advantages of DDR4 as opposed
to its predecessor, DDR3, include higher module density and lower voltage requirements, coupled
with higher data rate transfer speeds. DDR4 operates at a voltage of 1.2V with transfer
rates of between 1600 and 3200 Mbps, compared to data rates of between 800 and 2133 Mbps
and voltage requirement of 1.5 or 1.65V of DDR3. Although a low-voltage standard has
yet to be finalized, it is anticipated that low-voltage DDR4 will run at a voltage of
1.05V, compared to DDR3's low-voltage standard which requires 1.35V to operate. DDR4 modules
can also be manufactured at twice the density of DDR3.
Development and market history Standards body JEDEC began working on a successor
to DDR3 around 2005, about 2 years before the launch of DDR3 in 2007. The high-level
architecture of DDR4 was planned for completion in 2008.
Some advance information was published in 2007, and a guest speaker from Qimonda provided
further public details in a presentation at the August 2008 San Francisco Intel Developer
Forum. DDR4 was described as involving a 30 nm process at 1.2 volts, with bus frequencies
of 2133 MT/s "regular" speed and 3200 MT/s "enthusiast" speed, and reaching market in
2012, before transitioning to 1 volt in 2013. Subsequently, further details were revealed
at MemCon 2010, Tokyo, at which a presentation by a JEDEC director titled "Time to rethink
DDR4" with a slide titled "New roadmap: More realistic roadmap is 2015" led some websites
to report that the introduction of DDR4 was probably or definitely delayed until 2015.
However, DDR4 test samples were announced in line with the original schedule in early
2011 at which time manufacturers began to advise that large scale commercial production
and release to market was scheduled for 2012. DDR4 was expected to represent 5% of the DRAM
market in 2013, and to reach mass market adoption and 50% market penetration around 2015; as
of 2013, however, adoption of DDR4 has been delayed and it is no longer expected to reach
a majority of the market until 2016 or later. The transition from DDR3 to DDR4 is thus taking
longer than the approximately five years taken for DDR3 to achieve mass market transition
over DDR2. In part, this is because changes required to other components would affect
all other parts of computer systems, which would need to be updated to work with DDR4.
In February 2009, Samsung validated 40 nm DRAM chips, considered a "significant step"
towards DDR4 development since in 2009, DRAM chips were only beginning to migrate to a
50 nm process. In January 2011, Samsung announced the completion and release for testing of
a 2 GB DDR4 DRAM module based on a process between 30 and 39 nm. It has a maximum data
transfer rate of 2133 MT/s at 1.2 V, uses pseudo open drain technology and draws 40%
less power than an equivalent DDR3 module. Three months later in April 2011, Hynix announced
the production of 2 GB DDR4 modules at 2400 MT/s, also running at 1.2 V on a process between
30 and 39 nm, adding that it anticipated commencing high volume production in the second
half of 2012. Semiconductor processes for DDR4 are expected to transition to sub-30 nm
at some point between late 2012 and 2014. In May 2012, Micron announced it is aiming
at starting production in late 2012 of 30 nm modules.
In July 2012, Samsung Electronics Co., Ltd., announced that it has begun sampling the industry's
first 16 GB registered dual inline memory modules using DDR4 SDRAM for enterprise server
systems. In September 2012, JEDEC released the final
specification of DDR4. In April 2014, Hynix announced that it has
developed the world’s first highest density of 128 GB module based on 8 Gb DDR4 using
20 nm class technology. The module works at 2133 Mbit/s, with a 64-bit I/O it processes
up to 17 GB of data per second. Hynix expects DDR4 SDRAM to be commercialized by 2015, and
make it a standard by 2016. Market perception and prospects
In April 2013, a news writer at International Data Group – an American technology research
business originally part of IDC – produced an analysis of their perceptions related to
DDR4 SDRAM. The conclusions were that the increasing popularity of mobile computing
and other devices using slower but low powered memory, the slowing of growth in the traditional
desktop computing sector, and the consolidation of the memory manufacturing marketplace, meant
that margins on RAM were tight. As a result the looked-for premium pricing used for initial
profitability when introducing new technology to the marketplace, was harder to achieve,
and capacity had shifted to other sectors; SDRAM manufacturers and chipset creators were,
to an extent, "stuck between a rock and a hard place" where, according to iSupply, "Nobody
wants to pay a premium for DDR4 products, and manufacturers don't want to make the memory
if they are not going to get a premium". A switch in market sentiment towards desktop
computing and release of chipsets having DDR4 support by Intel and AMD could therefore potentially
lead to "aggressive" growth. Implementations
AMD will begin supporting DDR4 with the Hierofalcon SOC in 2014. Similarly, Intel's 2014 Haswell-E
roadmap revealed the company's first use of DDR4 SDRAM in Haswell-E CPU.
Technical description The new chips will use a 1.2 V supply with
a 2.5 V auxiliary supply for wordline boost called VPP,, versus the standard 1.5 V of
DDR3 chips, with lower voltage variants at 1.05 V appearing in 2013. DDR4 is expected
to be introduced at transfer rates of 2133 MT/s, estimated to rise to a potential 4266 MT/s
by 2013. The minimum transfer rate of 2133 MT/s was said to be due to progress made in DDR3
speeds which, being likely to reach 2133 MT/s, left little commercial benefit to specifying
DDR4 below this speed. Techgage interpreted Samsung's January 2011 engineering sample
as having CAS latency of 13 clock cycles, described as being comparable to the move
from DDR2 to DDR3. Internal banks are increased to 16, with up
to 8 ranks per DIMM. Protocol changes include:
Parity on the command/address bus Data bus inversion
CRC on the data bus Independent programming of individual DRAMs
on a DIMM, to allow better control of on-die termination.
Increased memory density is anticipated, possibly using TSV or other 3D stacking processes.
The DDR4 specification will include standardized 3D stacking "from the start" according to
JEDEC, with provision for up to 8 stacked dies. X-bit Labs predicted that "as a result
DDR4 memory chips with very high density will become relatively inexpensive". Prefetch remains
at 8n with bank groups, including the use of two or four selectable bank groups.
Switched memory banks are also an anticipated option for servers.
In 2008, concerns were raised in the book Wafer Level 3-D ICs Process Technology that
non-scaling analog elements such as charge pumps and voltage regulators, and additional
circuitry "have allowed significant increases in bandwidth but they consume much more die
area". Examples include CRC error-detection, on-die termination, burst hardware, programmable
pipelines, low impedance, and increasing need for sense amps. The authors noted that as
a result, the amount of die used for the memory array itself has declined over time from 70–78%
with SDRAM and DDR1, to 47% for DDR2, to 38% for DDR3 and potentially to less than 30%
for DDR4. The specification defined standards for x4,
x8, x16 memory devices with capacities of 2, 4, 8, 16Gib.
Command encoding Although it still operates in fundamentally
the same way, DDR4 makes one major change to the command formats used by previous SDRAM
generations. A new command signal /ACT is low to indicate the activate command.
The activate command requires more address bits than any other, so the standard /RAS,
/CAS and /WE signals are shared with high-order address bits that are not used when /ACT is
high. The combination of /RAS=L, /CAS=H and /WE=H that previously encoded an activate
command is unused. As in previous SDRAM encodings, A10 is used
to select command variants: auto-precharge on read and write commands, and one bank vs
all banks for the precharge command. It also selects two variants of the ZQ calibration
command. In addition, A12 is used to request burst
chop: truncation of an 8-transfer burst after 4 transfers. Although the bank is still busy
and unavailable for other commands until 8 transfer times have elapsed, a different bank
can be accessed. Also, the number of bank addresses has been
increased greatly. There are 4 bank select bits to select up to 16 banks within each
DRAM: 2 bank address bits, and 2 bank group bits. There are additional timing restrictions
when accessing banks within the same bank group; it is faster to access a bank in a
different bank group. In addition, there are 3 chip select signals,
allowing up to 8 stacked chips to be placed inside a single DRAM package. These effectively
act as three more bank select bits, bringing the total to 7.
Note: x bits are "don't care", but must be at a valid voltage level, either 0 or 1.
Standard transfer rates are 1600, 1866, 2133 and 2400 MT/s. 2666 and 3200 MT/s are provided
for, but the specifications are not yet complete. Design considerations
Some key points for IC and PCB design were identified by the DDR4 team at Micron Technology:
IC design: VrefDQ calibration;
New addressing schemes; New power saving features.
Circuit board design: New power supplies;
VrefDQ must be supplied internal to the DRAM while VrefCA is supplied externally from the
board; DQ pins terminate high using pseudo-open-drain
I/O. Module packaging
DDR4 memory comes in 288-pin DIMM modules, similar in size to 240-pin DDR3 DIMMs. The
pins are spaced more closely to fit the increased amount within the same 5¼ inch standard DIMM
length but, the height is increased slightly to make signal routing easier, and the thickness
is also increased to accommodate more signal layers.
DDR4 SO-DIMMs have 260 pins, which are also spaced closer, and are 1.0 mm wider, but
remain the same 30 mm in height. References
See also Synchronous dynamic random access memory – main
article for DDR memory types List of device bandwidths
SDRAM latency JEDEC page: Main Memory: DDR3 & DDR4 SDRAM,
DDR4 SDRAM STANDARD