Hello, welcome to this short lecture on analog-to-digital converter (ADC).
An ADC converts a continuous-time and continuous-amplitude
analog signal, such as the output of a sensor,
to a discrete-time and discrete-amplitude digital signal.
In the next couple of slides, I will talk about three important parameters of ADC:
resolution, quantization error, and sampling rate.
The ADC resolution is defined as the number of binary bits in the ADC digital output.
If the resolution is N, the output can be calculated by using this formula.
Here, the reference voltage Vref is the maximum input voltage that can be converted by the ADC.
For example, for 10-bit ADC, if the input voltage is 1 volt and the reference voltage
is 5 volts, then the ADC output is 205 in decimal or CD in hex.
The amplitude of the ADC input is continuous and has an infinite number of possible values.
However, the ADC can only produce a finite number of digital values.
Accordingly, the conversion process introduces unavoidable quantization error.
More specifically, the round function in that equation introduces quantization error.
For example, a 3-bit ADC provides a total of 8 different quantization levels, ranging
from 000 to 111.
The smallest change in the input voltage required to guarantee a change in the output is expressed
in terms of the least significant bit voltage (LSB).
The maximum quantitation error of an ideal ADC is 0.5 LSB.
For example, if the reference voltage is 5 volts, the max quantization error for a 3-bit
ADC is 0.357 volt.
Let's use another example to show the quantization error.
In this figure, the input signal is a sine wave, shown in green color.
Suppose the resolution of the ADC is 5 bits, and the ADC can accept both positive and negative
analog signals.
The output of the ADC is shown in red color.
The blue line shows the quantization error, which is the difference between the input
and the output.
As we can see, the quantization error is uniformly distributed between -0.5 LSB and +0.5 LSB.
We have reviewed the ADC resolution and quantization error.
Now let's talk about sampling rate.
The ADC sampling rate is defined as the number of output samples available per unit time.
In many digital signal processing applications, the sampling rate is usually fixed, and sampling
is triggered periodically after a fixed time interval.
What sampling rate do we need?
This question has been answered by a famous theorem called Nyquist-Shannon sampling theorem.
The theorem says: to be able to reconstruct the analog input signal, the sampling rate
must be at least twice the maximum frequency component contained in the input signal.
As shown in this figure, the input signal is a sine wave.
A sampling rate at less than twice the frequency of the sine wave will result in a loss of
information and fail to reconstruct the original sine wave.
In practice, we often use a sampling rate of 5 to 10 times the analog signal frequency.
There are three popular ADC architectures in use today,
including successive-approximation (SAR), sigma-delta, and pipeline.
Each of these architectures offers distinct performance advantages.
The SAR ADC is often considered the backbone of general-purpose mixed signal circuits.
Its resolution ranges from 8 bits to 20 bits, and its sampling rate can be as high as tens
of mega-samples per second.
SAR ADCs have ultra-lower-power consumption, and they are widely used in applications such
as control loops, power monitoring, and low-to-median frequency analysis.
Sigma-delta converters offer the best resolution but they are mostly for slow-speed applications.
Pipeline converters offer very high sampling rates, up to hundreds of mega-samples per
second.
They are often used in high-speed instrumentations.
A STM32 microcontroller often has multiple ADC modules.
These modules are based on the SAR architecture, as shown in this diagram.
For SAR ADC, each conversion process is divided into two phases: a sampling phase,
and a conversion phase.
The sampling phase is performed by the sample and hold component.
When the capture switch is closed, this capacitor starts to get charged, and eventually the
input voltage is captured in this capacitor.
The conversion phase begins immediately after the capture switch is opened.
As shown in the previous diagram, the sample and hold component consists of a resister
and a capacitor.
Software can program the sampling time, that is, how long should this switch remain closed
so that the input voltage is accurately sampled.
By the end of the sampling time, the voltage in the capacitor must be settled to the required
quantization error range.
The difference between the voltage in the capacitor and the input voltage should be
less than half of an LSB.
This is a fundamental requirement to obtain accurate conversion results.
A ADC module can support up to 16 input channels.
The sampling time of each input channel can be independently programmed.
Available sampling times are listed here, ranging from 2.5 cycles to 640.5 cycles.
After the sampling phase completes, the conversion phase starts immediately.
In the conversion phase, the ADC module uses a binary search strategy to find the desired
digital output.
One way to understand the binary search algorithm is to recall how to play the high low game.
You are asked to guess a secrete number, say, between 0 to 100.
At every guess, you will be told whether your guess is higher or lower than the secrete
number.
To minimize the number of guesses, we should select the middle value between the largest
and smallest possible numbers.
Accordingly, our first guess should be 50.
In this 4-bit ADC example, the conversion phase takes four clock cycles.
During the first cycle, the analog input is compared against 1000, which represents 0.5
times the reference voltage.
Since the input is greater than 0.5 in this example, during the second cycle, the input
is compared with 0.75.
In the third cycle, the input is compared with 0.625 because it was smaller than 0.75.
And in the last cycle, the input is compared with 0.687.
For n-bit ADC, the conversion phase takes n cycles.
In each cycle, one bit of the output is determined, starting from the most significant bit.
The total ADC time is the sum of the sampling time and the conversion time.
The conversion time takes N cycles, where N is the ADC resolution.
As discussed previously, the sampling time is programmable.
For example, if the ADC clock has 16 MHz and the sampling time is set to 4 cycles.
For 12-bit ADC, the total ADC time is 4 plus 12, that is, 16 cycles or 1 microsecond.
For 6-bit ADC, each conversion takes 10 cycles, or 0.625 microsecond.
This is the diagram of one ADC module.
Each ADC module is a 12-bit successive approximation converter.
Each converter can support a total of 16 regular channels and 4 injected channels.
The ADC module can convert up to 16 regular channels in any desired order.
Each channel can have different sampling period.
All regular channels share the same ADC data register.
However, each individual injected channel has its own dedicated ADC data register.
We have talked about the fundamentals of ADC hardware.
Now let's see how software should program ADC.
The ADC module supports several conversion modes.
In the single-channel mode, only one channel is converted once or repeatedly.
In the scan mode, a set of pre-defined input channels are sampled once or repeatedly.
Software can program the order in which these channels are sampled.
The next couple of slides give us four examples of retrieving the conversion results from
the ADC data register.
In the first example, software uses polling, or busy waiting to get ADC results.
Assume ADC is configured to make conversion once, instead of repeatedly.
Software first sets the ADSTART bit in the ADC control register to start the conversion
on the specified channel.
Then, software waits until the conversion completes.
When a conversion finishes, hardware sets the end of conversion flag (EOC) to 1 to indicate
that the result has been placed into the ADC data register.
Software uses this while statement to wait until hardware sets the EOC flag.
After the while statement, software can read the ADC result.
If more conversions are needed, software can repeat this process.
This busy waiting method is simple but very inefficient.
The second example uses ADC interrupts to improve the efficiency.
When a conversion completes, the ADC hardware generates an interrupt request if the ADC
interrupt is enabled.
Then, the processor responds to the interrupt request and automatically executes the ADC
interrupt handler.
The ADC interrupt handler reads the ADC data register (DR) and saves it into a memory buffer
for future calculation.
Note that hardware automatically clears the EOC bit flag if the ADC data register (DR)
is read.
That is why software does not explicitly clear the EOC flag in the interrupt handler.
Compared with busy waiting in the first example, the interrupt method is much more efficient,
because the processor is available to run other computation tasks during ADC conversions.
Many applications require ADC to make conversions at a fixed rate.
To meet this requirement, we can use the trigger output signal (TRGO) of a timer to trigger
ADC conversions.
You can review the short lecture on timer output compare to see how to program a timer
to generate a pulse periodically.
When ADC is triggered by a timer to make conversions at a fixed rate, there are two approaches
to get ADC results.
The first one is to use ADC interrupts as introduced previously.
As shown here, when a certain number of samples has been saved in the buffer memory, the ADC
interrupt handler can set the global variable ADC_Done to TRUE to inform the main program
that data are ready to be processed.
A more efficient method is to use Direct Memory Access (DMA).
When a conversion completes, the ADC hardware generates a DMA request to the DMA controller.
The DMA controller responds to the request by automatically copying the value of the
ADC data register to the memory buffer, without involving the processor.
After the DMA controller makes a specified number of DMA transfers, the DMA module can
generate an interrupt request to inform the processor that the DMA has completed.
The processor responses to the DMA interrupt request by executing the DMA interrupt handler.
The DMA interrupt handler can set the global flag DMA_Done to true to inform the main program
that data in the buffer are ready to be processed.
Thank you for watching.
Please visit the book website for more examples.
See you next time.