So
initially our topic, which was main flash memory so I parsed it into
basic key scaling challenges and future outlook.
So how do we make things that really what are the basics, how to make things today.
And then how are we going to make things tomorrow and the day after?
outline is a, a quick review of product trends, a device
primer, part of the basic flash, floating gate cell really work.
Technology scaling which is you have you are trying
to make things smaller and cheaper, better and faster.
How do we really do that?
One of the key challenges that we face in terms of scaling of
flash you probably are a little bit more familiar with standard schema scaling.
We'll try
to compare and contrast that with how flash
is scaled and then I'll summarize my talk.
so, What is flash memory most commonly used for?
So, we started off with tapes then we
went to discs, SD cards, now we have smartphones.
Please note, the smartphone I have here has Intel
[UNKNOWN]
architecture inside, I consider that is the best smartphone there is.
With my shameless feel for Intel out.
so we have a lot of things, music, video, phone, all that stuff.
It is integrated into a smartphone so, and a whole bunch us.
And I'm probably exaggerating but probably all of us have
a smartphone which is using a whole bunch of flash.
And the real key enabler for that kind of a technology has been flash.
So it's affecting our day to day life and it's kind of makes me pretty happy that
we can actually do that and still have fun doing all the technical stuff that we do.
outlook.
So flash TAM today towards the available market
is somewhere in the 27 billion dollar range.
Be expected to grow 2X in the next four or five years.
These are predictions so, all predictions have a hockey stick in the next future.
But these are predictions and we do expect.
And the real growth is going to come from like professor
[UNKNOWN]
mentioned, from SSDs.
So if you look at where we are today,
we have a pretty small fraction of the whole NAND
going onto SSDs and that's where we make money.
that's, the
[UNKNOWN]
ratios that we talk about in terms of people who
are actually using SSDs in their laptops is still very small.
It's not even at double digits yet so
you can see the opportunity to go is humongous.
I have a SSD, I've had it for the past five years and I'm sure professor
[INAUDIBLE]
has it too and it really can feel the difference.
It's much more rugged.
A whole bunch of things are much better about flash.
So, and that is the key, growth opportunity we see.
And it is expected to be the largest market
and we are seeing those trends even in industry today.
So yes, SSDs will be the next big thing
and computers will be the next big thing for Flash.
Which will keep the growth going, Going forward.
So before going into the next thing, which is a, like a device physics
primer, one thing is feel free to ask questions at any point of time.
Let's make this interactive, fun and so we
all actually get something out of this talk.
So feel free to ask me questions at any point of time.
basics of flash memory.
So, a floating gate flash memory looks quite a bit like
a transistor but with some key differences.
you have a PolyOne floating gate between what we usually think of as a transistor.
You have a tunnel oxide silicon dioxide for the tunnel oxide.
You have an interpoly dielectric, which is ONO, oxide-nitride-oxide.
And you have source/drain junctions which
are optimized for this particular operation.
So you can electrically have a poor circuit saying you have a transistor.
Which has a floating gate node and it couples
to the entire world around it through difference capacitancies.
For example, it couples to the drain, it couples to the
source, it couples to the substrate as well as the control gate.
Electrically pictorially des described as a dark line between the gate and
the substrate.
the fundamental property of a flash cell is essentially, can be
boiled down to just one, which is a gate of link ratio.
And you want to maximize this as much as possible.
so it'll be how much the control gate controls
your floating node, as opposed to the entire world
that controls your floating node So you notice that
as we go along and I talk about scaling
challenges, it is this parameter that degrading as the rest
of the parasitics are controlling the floating gate more and more.
How does a flash work? Pretty straight forward.
You put electrons, or you take away electrons from the floating gate.
programming means putting electrons on and that pushes your threshold voltage high
because you need that much higher gate overdrive to actually get inversion.
And erasing means removing electrons from the floating gate,
and that gets you to the Low Vt state.
the more of electrons that you put Is
very proportional to the Vt shift and it goes through
the control gate, or the CIPD that we have there.
So you can notice that for a given
threshold voltage shift if your capacitance starts going down.
You're going to need smaller and smaller number of electrons to actually program.
Which becomes a pretty big scaling limiter also.
NAND and NOR.
I'm sure basics of NAND and NOR are pretty known.
So wanted to have a differentiate its life but I'm going to skip that for skip.
We have two most popular types of NAND, which
are NAND and NOR, the equivalent secondary we talked about.
Really big differences in the way things are connected electrically.
In a NOR cell, each cell is actually connected to
the Bitline directly.
With the source being common to the whole block.
I started working in NOR's.
It was pretty nice that I could actually go
and measure a single cell when I was trying
to make arrays and products, sort of that, so
I could exactly know the idea of that cell and.
Being connected allows me to do that.
But when you go to NAND, what you
see is is essentially a string of serially connected
cells current state of the art is about 64 and
people are playing with 128 cells in a string also.
it's connected to a bit-line through a select transistor.
So, you're trying to make a whole bunch of these NAND transistor, but you
don't really have access to the source or the drain of an individual transistor.
When I really started working on this, it was pretty worrisome
to me that I don't know how a single cell behaves.
How am I going to create a whole bunch
of gigabyte kind of areas.
and it does pose a problem but you can figure out
ways around it to actually get the electrical information that really want.
in terms of a cross section, you can see the same thing pictorially
where an old cell for every cell that is a drain contact and source.
Every cell has a drain, contact and the source.
So you have access to each and every cell, where as
in a NAND cell you have two select transistors at the end.
And you have a whole bunch of lines and spaces
which as a string of 32, 64, 128 strings in
the middle that you don't really need to access.
The strength of having, not having contacts for every cell is lack
of an individual cell results in a very small N and site.
So we are very close to the fundamental or actually even beyond the fundamental
than the 4 lamda squared, the smallest
dimension that can be printed and resolved.
yes the select gates are overhead so
you can see you have two select gates for x number of strings.
And like I mentioned, the trend is to go
bigger and bigger in terms of the string length.
And the soul reason for that is to amortize
the select gate overhead over larger number of wave length.
So, this overhead just keeps looking smaller and
smaller, as you go to larger and larger strings.
And that isn't very good to longer string length.
So
not having contacts really make this an extremely area effecient
technology.
So, the fact that you have bit access verses not
Leads to very different applications in the floating ate structures.
Nan is essentially a dominant memory for data storage because it can
provide very high throughput and very high density and a very low cost.
it is not something that you can access one
bit and suddenly the whole access time scales down.
It pretty
much takes you the same time to access one bit.
As 16K bytes.
So, random access is very slow, so you can't really
use non for, executing place or any of those things.
now on the other hand, is, mainstream for code storage.
And, it can, it has very.
Fast random access program, and very suitable for code applications.
It is less suitable for data storage
because it has low throughput and because of
the contact of each cell, it is very area inefficient, so it's higher cost as well.
a Khartoum cross-section essentially is as simple as it really gets.
You have board lines and brick lines in checkerboard fashion.
And that's the heart of a flash cell.
so equivalently you can see you have brick lines running across the whole block.
Your word lines running across word lines, and
you are making a cross point, in some sense,
a cross point array that where you have a
transistor between a word line and a bit line.
And to the word line transactions you've already looked at it.
you have word line source, word line source, and
that's the way the string works, and in the other
direction you have a floating gate followed by a wrap of the board line.
So we talked about properties.
We talked about how the structure looks like.
So, let's change gears and go into how
basic operation of the NAND flash really works.
So you need to do only three things with any memory.
You want to write it, you want to erase it and
you want to be able to read what you just wrote.
So, let's start with a read.
How do you really read a NAND flash cell.
Especially since I mentioned a few minutes ago
that I don't have access to a particular cell.
It's pretty much like a, if you tried to read a NAND circuit.
So, the cell that's you're trying to, read.
Is save the blues cell that you're trying to bleed.
We want to take all the rest of the cells out of the equation.
So we apply a high voltage on the rest of the
volt line to make them essentially pass down the stairs, which as
with as low of a voltage drop as possible. So that's how you bias the array.
You want to make the cell, target cell to be the determinant of the entire
resistance and the rest of the string has to be as low resistance as possible.
You charge up the bit line.
you select essentially the particular string.
This is kind of an important thing especially
if you're trying to build array, that you can select
a block and keep the rest of the blocks deselected.
That way your data is essentially telling you what this block
is intending on getting any disturb signals from L, from other blocks.
And keep the selected wood lines at zero, and if the
cell V T was programmed which is of high V T.
Sorry this string is this string is not going to conduct any current
and you know that the cell that you are talking about is indeed programmed.
Well as the salvity is less than zero, it's going to discharge the
whole bit line and you're going to be able to sense that as well.
here you can see that I want from a, a operation point of view, I want
to apply as high a passive is as
possible so that the passive distance becomes very small.
But there are practical limits because once you
go to a very high limit, a very high
voltage you're actually going to start self-programming the cell
and that'll lead to a disturb like a re-disturb.
So that's the boundary that we are always trying to play
that you want to be as high as possible for functionality but
low as possible from a reliability point of view.
in the earlier recording, I showed you two cells.
So that would be a single level cell.
So you either put electrons, or you don't put electrons in the cell.
And that's how, that's the number of gigs you get.
You can go kind of crazy about that idea
extrapolated to as many level set as you want.
So a cellsea is not really, that much, that
common these days, it's quite expensive and that's the name
of the game and that is essentially cost.
a cellsea offers a very high performance but does not go anywhere in terms of cost.
So MLC, where you are actually putting four levels instead of
the two gives you 2 bits in effectively the same area.
So, it straight up drops your cost by a factor of 2.
There are some overrides involved that I need to be a
little smarter with the way I make a die when I'm
doing MLC versus SLC. So the savings is not directly to x.
But you do get, very large saving when you go from, SLC to MLC.
What you do observe is that the difference
between a program and arrays shrinks dramatically down.
So you have the ability to put many more levels
but now, it has come into a cost of A,
programming and B, reliability.
And you can keep extrapolating that further
so you can have actually three cells.
You'll notice that you have to go and, and commence of two to the power n to
actually get three bits and four bits into the
level, and the separation actually scales down much faster.
So one versus three versus seven, so it scales down much faster.
But it's possible to do it.
On the right, again it's one of our products.
It's a
[INAUDIBLE]
per cell part of from 25 nanometer node, I think we published it a couple years ago.
it clearly shows you can do this.
You can have
[INAUDIBLE]
distribution which are very fine.
We can cycle it well, its performance is well.
So, it's doable.
But the effort it takes to make this is significantly higher
than what it takes to make just a two bit part.
So, putting more levels great idea, comes
at a pretty high engineering cost involved there.
[COUGH]
So it all comes down to what is good enough.
MLC can become good enough and then suddenly
there is going to be no demand for SLC.
And either DLC can also become good enough
and then again you'll have no demand for MLC.
Because to make it it becomes cheaper.
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