welcome to the HDL coder video series in this video series we will learn a
popular production proven path to take a MATLAB digital signal processing
algorithm through similan fixed point designer and HDL coder to target an FPGA
in the first part of the video series we discussed the strengths of MATLAB and
Simulink and provided an overview of the HDL
coder self guided tutorial available on the math works file exchange website in
the second video we created the Similan model hardware implementation of the
pulse detection algorithm in this part we will prepare the Simulink model for
HDL code generation and highlight techniques to optimize the hardware
microarchitecture we will rename and save the model
and run the HDL set up on the MATLAB command line HDL setup configured
several model parameters for HDL code generation one of the parameters sample
time corresponds to how fast a region samples data and this is visualized by
means of color code on an FPGA this often translates the clock rate how fast
data gets clocked through pipeline stages which coordinate the timing of
signals as they traverse parallel paths blocks with varying sample times appear
in different color and the model is updated in our model the sample times
are the same and on updating the blocks and signal lines will appear red
combined the filter block compute power and local peak subsystems into a top
level subsystem and name it pulse detector this new subsystem will be
referred to as device under test or DUT and contains the algorithm for which V
will generate the HDL code HDL coder software provides architecture options
that xn control over speed and area trade-offs in realization of hardware
designs we will show multiple ways of inserting pipeline stages to balance
parallel paths and run at a higher clock frequency we will start by changing the
filter structure to direct form transpose to result in better timing
performance and insert additional input-output pipeline registers
similarly add one level of input and output pipeline registers and set
adaptive pipelining to on for the compute power subsystem
via the HDL block properties adaptive pipelining automates the insertion of
pipeline registers for certain operations which results in improvement
of the clock speed the increase in clock speed is achieved by having less logical
operations between pipeline stages this optimization technique is dependent on
the target device and frequency settings when we generate the HDL code from the
model at the final step we can view the delays inserted in the various blocks
the pipeline registers affect the overall simulation of the model and to
simulate the effect one can manually insert the delays which is what we will
do when we add a data validity check as a control signal in the Simulink model
design we create the valid in and valid out ports and add pipeline delays to the
parallel parts one on the data input output path and the other on the valid
input output path present in the DUT subsystem log the valid in signal after
the delay block as the filter valid signal to qualify the output during test
using the testbench script pulse detector v2 TB we compare the output of
the MATLAB golden reference and the updated Simulink model the logged filter
valid signal validates the output of the filter and magnitude squared blocks in
the testbench script the output data from the test bench proves that the
Similan model after optimization for HDL code generation matches the golden
reference in the third part of this video series on the HDL coder we have
made changes to the Simulink model for HDL code generation and emphasized the
techniques available to optimize parameters to improve speed and resource
usage in the next video we will convert the Simulink model design to fix point
data types