SDI. So, let's take a look.
This is that same a6 microprocessor, which came out a few weeks ago.
So you can see these are all your P-type, or maybe N-type transistor.
Then you have this SDI That you form, which is separating
them from anti-abrasion, which is somewhere else, not in this picture.
So once you have formed these two regions, which are, you have formed, you
have decided I'm going to make my n-type
transistors here and your p-type transistors here.
The next thing to do is impline them such that they become p-type or n-type, right?
So, you do well, implants.
And these are, these are typically
the highest energy implants, because you're implant.
and so you put a sacrificial
oxide, because you implant with such a
high energy, you don't want to damage your substrate.
For the sacrificial oxide that you put and then
many times you use not one implant but multiple implants.
And and then you do this for your p-well. Then
you do the diverse mask and you color your p-well and you explore your n-well and
if it's a n-well you employ red phosphorus or arsenic, right?
And then you anneal them together, so you they are activated and you have your P
well and your N well region defined. Alright?
So the next step is your gate oxide growth.
This is typically your gate oxide is your most critical oxide, so.
At most care is taken when you're growing this.
So it's typically a, a, thermally grown oxide, not a deposited oxide.
So it's, it's done in a RTP chamber.
Where you can grow it in a, in an oxygen plasma, in an oxygen environment.
Many time people nitrite it because that helps, first
of all it helps in improving your dielectric constant.
And it also
improves the defu, barrier property of this oxide, so it helps
boron from diffusing into your electric. Later,
in week five, we'll actually discuss the HI K meraricle flow and how.
so that comes in a displace If you're doing a
gate first process, then you deposit HI K over here.
if you're doing a gate last process, you move on.
And then you deposit your polysilicon gate.
So, this is a amorphous polysilicon gate, blanked into position across your wafer.
Again, you want to etch it so you want to before
you etch it, you need to make a hard mask.
So you, in this case, you can use again
a hard mask.
some people would prefer to use this carbonate hard
mask because they can very easily etch it off.
But you put a hard mask, you put a resist. And
you pattern that resist into the gate lines you want to form.
You transferred that pattern from your resist into your hard mask.
And then you etched that pattern into your polysilicon.
Alright, and this is typically the most critical edge
that happens in the entire process because it's at
the very finest feature at the same time you're
etching a poly region and stopping on a dielectric.
And when you're etching it's very difficult
to stop on dielectric especially if it's like a one nanometer tin dielectric.
So if you do this etch and you get get it right then you
you have achieved a accomplishment, which is worth taking a picture.
And if you take a picture at this point
of time, it, it, it looks something like this.
So, for a 65 nanometer process, it looked something like this.
For a 45 nanometer, you can see the lines are in fact.
More rectangular and you can see the corner is even better.
>> When using SOI,
the top silicon layer, is that like defect-free?
>> The top silicon layer is defect-free, yes.
>> How do you make that top layer? >> Typically people deposit so these are
Okay, since you ask, let me show you. This is a, a process for making SOI.
So you start with a wafer then you implant it with hydrogen.
It's called a smart cut process.
And then you put it on top of a handle wafer and
then you can cleave where the hydrogen was implanted so it's a.
That's why it's called a smart card because where
you implant it with hydrogen you can clear it off.
And that, that top layer is defective because you know,
it was implanted and then it had all the defects.
But then what you do is you polish it.
So you polish it off that defective layer and you take
tin it down to the required thickness, which is defect free.
Typically you're implying something like 200 nanometer thick.
And then you just thin it down to the very 20,
50 nanomete,r which is defect free.
So a question I had here was why did actual lines become uh,
[COUGH]
better from 65 to 45.
So the these then they became rectangular,
while over here, you're actually printing with rectangles.
When people move to 45 they actually, what they
did was they used to print in two steps.
You print straight lines.
So they are actually pattern, all of them straight together and then
there are additional printing done and you cut them where you need to
cut them.
So it's two mask instead of one to make the same feature.
That's why they look more rectangular.
So we, we have a lecture on Wednesday where the
person who is responsible for doing this will come here.
He'll come and speak to
us.
The next step you do after, after you've form after you've done your
gate patterning is you need to form your source and drain junction, right?
So you need implants. And you need more than one implant.
There are three essential implants which are needed.
One is called a halo implant.
So if it's an NMOS, that means it's made on a p-type subtray.
This halo implant is off the same type, so it's a p-plus implant.
And then you do a cells drain extension implied.
So this one is of the opposite polarity, but n-type implant.
But it's low in doping.
So n-minus implant.
So minus means low, plus means high, right?
So it's an n-minus implant.
Finally, you have the source drain large region, which is an n plus implant.
So, so why do we need three implants, right?
So, we, why do we need this p plus and why do we need this n minus.
So the reason for that is, we want to minimize the short channel effects.
So we have a junction here, this is a p n junction.
This is p, this is n, right.
So we want to minimize the junction depleting
under the gate so we want to minimize our depletion work going
inside the gate. Because that will essentially eat up our
gate length. And I'm borrowing some knowledge from from
212, 216 here. For your junction for any PN junction,
your depletion on either sides, depends upon how much
doping you have on either side.
So if you are if you have a PN junction, your depletion
rate inside the P region is inversely proportional to the doping in that field.
So, if you have higher doping you'll
have less depletion in that particular region, right?
So it's w n and then what's the proportional
to the square root of doping in that region.
So, if you only
have less depletion worth in that particular
region you need to have more doping.
If you have less depletion inside your gate,
you need to put a higher doping here.
And that's why you have this P plus in front and you have this M minus implant.
Because you want to, the source, within reason, to deplete
in this direction, rather than deplete in this direction, right?
That's why you have this fancy
implant scheme and the way it is done is all you need three implants.
So you first implant, that is typically done is an extension.
And the way it is done is all you need three implants,
so you first implant, that is typically done is an extension implant.
So again you open up the region where you have your your
p-mos transistors, And this your,
sole strain extension implant. It's, low energy implant.
It used to be low dose.
So it used to be called LDD or low doped drain.
But now it's not that low a dose because if you go
very low in dose or if you go very low in doping.
Then you'll have a way higher resistance of that.
So that this is the next important step,
so that you have a sole train extension implant.
Then you implant these pockets, so you implant these pockets and
these are your halo implants.
And the way this implant is done is, you need to implant it at an angle, right?
So you hold your wafer at an angle. And, this is your ion beam coming in.
And then you rotate your wafer, you rotate it like all, 360 degrees.
So it gets this implant at an angle. So that's how this halo implant is done.
so people became so sick and tired of doing this implants
that one of the reasons for moving to FinFet for that.
You know, it became sort of difficult to control these implant.
So precisely that you form these junctions.
And and we'll discuss later going to a 3D transistor or a
finFET transistor that simplifies this soldering extension or
your soldiering appliance quite a bit.
So then you do the same thing on your end vision, so
you implant your end soul train extension. And then
you do your halo implant over here, and then
Then, what is done is, now you have done your halo implants.
You have also done your extension implants.
Now, you need to do these deeper implants, which are
your source and drain actual source and drain high doping implants.
And, you won't want to damage the region that you already implanted, so you.
You know with all this rotating wafer and using
I implanted on this region now, I, I want to protect them, right?
So what I do is I make a spacer.
And the way we make a spacer is the same way we make a spacer in lithography.
That is you deposit, you have, you already have a featured service,
so you have this Polygate, which are printed, so they're forming this feature.
And you deposit this nitrite layer conformity on your feature.
And then what you do is you
etch it from the top, so you etch it from the top.
So you suppose you deposited five nanometer, you'll etch
five nanometer here, you'll also etch five nanometer here.
So it's gone from all the horizontal surfaces.
The surfaces, which are left are these vertical surfaces.
Which is why it's called a sidewall, it's, that's why it's
called a spacer or a sidewall spacer to be more precise.
You have this spacer and this spacer it helps us to do this next set of implants.
So now we again cover it with photo resist.
We open up the region where you have p-feds and you do this higher energy
implant. Then you open up this, so this is showing,
this was our shallow implants.
And now you do this higher energy
implants, you have this deeper region, right?
Similarly, in our in our
so we do the same process both on P and N type.
And then, what you do is, you do a anneal process.
And the way this anneal process has been evolving was,
it used to be a furnace anneal, where you could Load
up a batch of wafers in a furnance and I
need them together but it used to take hours of time.
And the, the way things have been evolving here is all these
means to shorter and shorter time. So from furnance people move to RTA.
Then you move to a spike anneal, which is like,
[INAUDIBLE]
of a few seconds, then people move to a millisecond anneal.
And now we want to go to a nanosecond anneal numelators.
And the modulation for that is again, you
want to control the diffusion of your junction.
So you want to control how deep or how shallow you defuse.
The more slower you are on time, the more shallower your
junction is.
So that's why things have been evolving to slower and slower means.
Not slower and slower, higher temptrature. shorter in time menus.
So assembly at this point in time, we have formed our transistor, so
other things that we needed to do in our semiconductors have already been done.
And so actually coming back to the architecture,
that picture was taken at this point of time.
So that's why it had those lines. But outside this base is around it
so you cannot see the active regions very clearly because of the spaces.
But if you remove that then we can really see
that they are V lines are wider than your A lines.
[BLANK_AUDIO].
So at this point, we have essentially formed all
our other thing were to form inside our semiconductor.
So the next thing is to have a connect these transistors to the outside world.
So all the interconnects are made all right.
So we need something that connects
those interconnects to our semiconductor material.
So the material for that is silicide, which is essentially a mixture of
metal and
your, metal
and your semiconductor. And the way it's done is you
deposit a metal, in this case nickel, and this is a
Deposit wafer, if you have a small feature if you
don't have too high aspect ratio, you can do a PV to the position.
And then you anneal it.
And when you anneal it, this metal interacts
with your semiconductor and it forms a silicide.
So it only reacts at the places where
there was material available it, for it to react.
So it reacted on the top of your gate.
It reacted with this polysilicon to
form the silicide. At the same time at these, on top of your
sois and drain it again reacted with the the silicon in
your sois and drain to form this But
it did not react with the nitrite. So it does not react with nitrite.
So where your spacer was, you are certain and react to nickle.
So this is a very cool process that
try, it's a self aligned process hence the name.
salicide, which stands for self aligned silicide.
So this, this is a pretty cool thing, right.
It helped us to form these uh,soldering junction.
It also helps to these to do, to form our gate and soldering together.
And, essentially, what we
do next is simply dip it in a a
wet etch, which will remove all your un-reactive nickel.
So, the nickel on the spacers, you can easily remove,
and what you're left with is your contact on your.
Source and your drain.
important point is that at this point
you're pretty much done making your transistor.
And you don't want to go higher in temperature beyond this point, higher
than 450 the same temperature beyond that time because of multiple reasons.
If you go higher in temperature, you'll defill all these implants further.
At the same time, this nickel, this silicide, it has
this mono silicide phase, which is stable only after 450 C.
So special caution that is
given to the people who do processing.
Beyond this time is whatever happens don't go higher than 450 temperature.
So this is how it looks like after we have done
all this process steps. So you can see that there are five
devices, had two of them are PFETS. Three of them are NFETS.
And then you put a nitride around it this prevents from anything diffusing in.
Some people use to use it as
a stressor but now there's not enough volume of that nitride left so it's not
used as a stressor anymore. then you fill it up with another oxide
and then you planarize this oxide and Too much front end of the line
of process flow is, is done over here.
[MUSIC].