Hello folks.
So, what I want to do in this video is to talk a little bit about
the NAND Array, that is how are these
different, flash memory cells connected together in a array.
And, I also want you to understand this term that you often, see in
the news today, the news, news articles
from SanDisk, announcing their 19 nanometer memory.
So when they say 19 nanometer, they say
this is produced using this 19 nanometer manufacturing technology.
And this article claims that this is
the world's smallest chip at that particular time.
It's based on this 19 nanometer technology.
So, when they say this 19 nanometer technology, what does it mean?
Does it mean that their cell is size 19 nanometer
by 19 nanometer?
does it mean that this is the distance between two word-lines?
does mean that this is the distance between two bit-lines?
So we will answer these questions also, when we look at this NAND array.
So let's let's look let's look at you know, what you mean by a NAND array.
So
array means there'll be a bit-lines and there'll be word-lines.
And that would form your NAND array.
And, so what you do first is you define your, bit-line.
That's how a NAND array is defined, you first define these, bit-lines.
And these are essentially running parallel to each other.
And they are etched into your silicon.
So this blue thing represents silicon over here
And they are etched into your silicon.
And they are
separated from each other using this shallow trench isolation.
So these bit-lines are separated using shallow trench isolation.
And then what we do is we come on on top of and we form
these bit-lines, we form these word-lines, which run
perpendicular to these bit-lines. Essentially what you call as your,uh,
control gate so these would be your control gates,
running in this, particular, perpendicular direction to your, bit-lines.
And now we have essentially an array and
suppose, we want to address, one particular cell.
We select, say, a bit-line, one.
And, we select, all the transistors, on this,
on the other bit-lines, such that they turn on.
And we select this particular word-line, And
that would select, this particular, flash memory cell.
So, and the cross section of each of
these, bit-lines and word-line, there's a flash memory cell.
So there's a flash memory cell over here.
If you see a bit-line n. And this would be say, word-line three.
So, intersection of these would have a flash memory cell.
And each of these will essentially look something like this.
So you will, it will look something like this.
So you have your silicon from your bit-line.
And you'll have this control gate which will be forming your, word-line.
And in between you'll be having this, floating gate
into which you can, store charge and, erase charge.
And that way you can,
control the state of that cell.
So when we look at this flash memory array, again it's a, it's a, intersection
of these intertwining bit-line and word-line, so
it's important to look along at different direction.
If we going to look at how does this array
look along, this direction, meaning this direction along the bit-line.
And then how does this array look along this direction, that is the direction
along my word line. So let's look at a few cross sections.
First, I want to show you a cross section along the bit-line.
So, shown here is a cross section along the bit-line.
So, if you look at this array along the bit-line, so these are the blue
colored lines are my bit-lines. And I'm taking a cross-section
over here.
So what I immediately realize is this,
this cross section I'll have these multiple transistors.
Which are connected flash memory cells.
Which are connected in series.
So what I expect is essentially these Yeah, each of these flash memory
cells and I denote a flash memory cell by the symbol so this is a floating gate and
then this a control gate.
So each of these flash memory cells is connected in series with each other.
This shows here another picture which shows the same thing, so it
shows these different flash memory cells, which are connected in a NAND string.
So this is one flash memory cell, and this is
another flash memory cell, this is another flash memory cell.
And they are sharing these junctions
between each other.
So, this is a common source or drain between these two
cells, and this is a common source or drain between these cells.
And this is how it would look like if I take a cross-section over here.
And in fact, this is a, showing actual a, a cross-section across along these
NAND of these NAND array along the, along the bit-line direction.
So you can identify
these transist, these flash memory cells. So, another important point that
I want to make is these alternate transistors or these
adjacent transistors along your along my bitline.
They can very well be seperated or placed very closely.
So this distance between these two transistors
on a particular bit-line could be as low as the feature size.
So, let's say if your feature size is 19
nanometers, this distance can in fact, be 19 nanometer.
And these are cross section along of these cells.
could be 19 nanometer as well, so when we saw that
announcement from SanDisk saying that their technology is 19 nanometer it is
very well possible that these lines would have
been placed 19 nanometer apart from each other.
So, whenever we look at these cross sections of an array it's important to
look at both directions so I'll show
you the cross sections around bit-line direction.
It's also important to look at the cross section
perpendicular to it, that is the direction of my,
word-line.
So I'm showing you a cross section, along the word-line.
So, as I mentioned, these different word-lines are, etched into the
silicon so this would, these different bit-lines are etched into my silicon.
So this would be my bit-line one and this would be my bit-line two
and, and then they are separated from each other using this shallow trench isolation.
So you can clearly see this
this trench which is separating my alternating bit-lines.
And it's etched into the silicon and then it's, filled up, with an oxide layer.
And, this trench has a very high aspect ratio, it's, 217 nanometer deep.
And these are different bitlines, you know,
so this, this distance could be anywhere
between say, 30 nanometer So this has a very higher aspect ratio.
And then you can see this word-line which
is the wrapping on top of these different cells.
So your this is a cross-section along my word-line.
So I see this word-line wrapping on the top.
And let me take further
zoomed into view, zoomed in view and look into into
how the transistor, along along the word line look like.
So now I have a, completed forming my cell and I have
these different bit-lines and I can see them over here.
So this is my Bit-line this could be
my bit-line one, this could be my bit-line two.
And these are made etched into my silicon and then
they're separated by this shallow trench isolation
so I can still see the upper part of this shallow trench isolating
isolation. Which is separating these adjacent cells,
and then I can see over here my floating gate.
So this is my floating gate. But the interesting part is now that my my
word line, so this is my word line, so my word-line is wrapping around my cell.
So what I see is my word-line is wrapping around my cell.
So what I see over here, so this is the floating gate.
And then you have this
ONO stack so you can let me label it over here.
So you, this is your Floating gate, and this is your inter-poly dielectric.
This your tunnel dielectric.
And this interpoly dielectric is consist of this O-N-O, and you can
see the contrast different between them. So this would be your oxide.
And you have a nitride and your oxide. And then you have this word-line which is,
in this case made up of poly silicon. And you see your, your.
Word-line in this ONO, or your IPD, it's wrapping around your
wrapping around your floating gate cell. So the reason why, it,
is, done so is because you want to increase your coupling between your
floating gate and your control gate. So if you wrap it.
If your, if you have a floating gate and then you wrap around your control
gate so it gets you know, you surround it along three directions instead of just
one So you get higher capacitance of, with your control gate.
And our GCR, Gate Couple Ratio which is a key term which
is defined by this coupling that you get with your control gate.
Divided by the total capacitance of your floating gate, so that stays
high, because now you are getting higher capacitance with this control gate.
So that's
the reason we do this wrap around. And shown here is another picture which
shows the zoomed in view of this this one of these
transistors and along the word line direction.
So you can see that this is my floating gate and
so and this is my tunnel oxide and this
is my O this is my N and O labeled over here as ONO as well.
And my, both my inter-poly dielectric, and my, control gate is
wrapping around my, my floating gate. And
that is, intentionally done to increase my, gate
coupling ratio. So this helps in, in improving our
gate, coupling, ratio. But that, comes with, two disadvantages.
The first disadvantage that I want to mention is that
your IPD orthis, inter-poly dielectric will have certain thickness.
So, in this case, as you can see, this IPD
has a thickness of let's say you know, let's say 12 nanometer.
So, and, if I'm wrapping around, this IPD around my two cells.
The distance between my cell has to be atleast these two IPD thickness.
So, there has to be atleast, 12 times two distance separating over here.
So, this distance has to be, greater than atleast, twice
of my thickness of my inter-poly dielectric, for this to wrap
around my my my floating gate. So this distance is typically larger.
The distance between two adjacent bit-lines has to be has
to be at least twice more than the IPD thickness.
So this distance is typically, you know, in the range of
anywhere between, you know, 26 to 30, 35 kind of, nanometer
range.
And this distance between the word-line, this can be actually smaller it does
not involve a wraparound, and this could be in fact around 19 nanometer.
So this is one of the disadvantage of doing
this doing this wrap around of my control gate.
We have another disadvantage that you'll get in terms of, scaling that
that I'll talk in the next video.
But, the next time somebody, you know, you
meet somebody from, SanDisk,or, Micron or Samsung or
Intel and then say, they say, you know,
we have launched this, technology which is 15 nanometer.
And then you can say to him, you know, do you
mean 15 nanometer along between two word-lines or do you mean
15 nanometer along between two bit-line and you can
say, you know, I don't think so, it's 15 nanometer.
And you can tell him why and maybe you know, you can
have an inter, intelligent conversation over a cup of coffee with him.