This lecture explains how to use a timer to generate PWM output signals.
A timer is a hardware component, built within a processor chip.
Each timer has a special register, which is called the timer counter.
The counter runs freely.
If enabled, it automatically counts upwards or downwards, under the driven of a clock
source.
Pay attention.
It is hardware, not software, which keeps repeatedly incrementing or decrementing the
counter value.
For each rising edge in the clock signal, hardware increments or decrements the counter
by one automatically.
That is why we say timer counter is a free-running counter.
By modifying the PSC register, we can feed the counter with clock pulses at the rate
we desire.
The PSC register holds the frequency pre-scaler value or the frequency divider.
Before the input clock is fed to the counter, the frequency of the clock source is divided
by a constant integer, which is PSC plus 1.
The prescaler enables a tradeoff between timer resolution and timer range.
High timer resolution requires a high clock rate.
However, high clock rates cause the timer to overflow or underflow more quickly.
When a timer is configured to generate an output signal, hardware constantly compares
the free-running counter, with a value stored in a special register called the compare and
capture register (CCR).
The output of the timer, OCREF, can be high or low, depending on the timer settings.
As the name suggests, the CCR register has two usages, including compare and capture.
When a timer is used to generate output, the CCR register is used only for compare.
A timer can also be used for input capture.
When a specific external event occurs, such as a rising edge of an external signal, hardware
automatically copies the current value of the timer counter to the compare and capture
register (CCR).
We can use such an ability to measure the timing information of a signal event, such
as rising edge or falling edge.
In addition, to measure the external signal interval, two consecutive captures are needed.
We can calculate the period or the pulse width by subtracting these two CCR values.
In this lecture, I will focus only on the output function, instead of the input capture.
Specifically, I will show how to program the timer to generate a PWM signal.
We can configure a timer to repeatedly count up, count down, or count up and then count
down, in response to the clock signal.
Let's first take a look at the up-counting mode.
The auto-reload register (ARR) holds the maximum counter value, which is also called the auto-reload
value.
The counter counts from 0 to the auto-reload value, then restarts from 0, and generates
a counter overflow event.
This figure shows an example of the counter behavior when ARR is 6, and the repetition
counter is not used.
In the up-counting mode, when the counter has reached 6, it rolls over and is reset.
When the counter resets, it triggers a counter overflow and an update event (UEV).
After that, a new period starts.
The counting period is determined by the auto-reload value, as well as the clock period.
Specifically, the PWM period equals to one plus ARR, times the clock period.
In the down-counting mode, the counter counts from the auto-reload value (ARR) down to 0,
with respect to the pulses of the clock signal.
After the counter has reached 0, hardware automatically reloads the counter with the
auto-reload value, and generate two events, including a counter underflow event and an
update event.
The period of the down-counting mode is exactly the same as the period of the up-counting
mode.
In the center-aligned mode, the counter counts from 0 to the auto-reload value minus 1, and
generates a counter overflow event.
Then, the counter counts from the auto-reload value down to 1, and generates a counter underflow
event.
After that, it restarts counting from 0.
In this mode, the counting direction changes automatically on counter overflow and underflow.
For the center-edged mode, the period equals to 2 times ARR times the clock period.
PWM has two modes: mode 1 and mode 2.
In mode 1, the output is high, if the counter is less than the Compare and Capture Register
(CCR).
Otherwise, the output is low.
Mode 1 is a low true mode.
I will show an example output of PWM mode 1.
Suppose CCR is 3.
Here is the PWM output OCREF.
When the counter is less than 3, the output is high.
When the counter is higher than or equal to 3, the output is low.
As result, the duty cycle is 3 over 7.
As discussed previously, the period of this PWM signal is 7 times the clock period.
Software can set the PWM frequency by modifying ARR register, and change the duty cycle by
modifying CCR register.
Typically, a single timer can generate up to 4 PWM signals, with independent duty cycles
and identical frequency.
Each timer has four channels.
Each channel has its own Compare and Capture Register: CCR1, CCR2, CCR3, CCR4.
These four channels share the timer counter, and the auto-reload register (ARR).
Therefore, these PWM outputs have exactly the same period.
However, their duty cycle can be different because the value of these CCR registers can
differ from each other.
In the up-counting mode, when multiple PWM signals are generated by the same timer, all
rising edges occur at the same time.
That is why the up-counting mode is edge-aligned.
This example shows the PWM output when CCR is 3 and 6.
All rising edges of the PWM signals are aligned with the overflow events of the timer counter.
More specifically, the PWM outputs are left edge aligned, because all pulses are aligned
to the left side of the PWM period.
The outputs go to their active state at the beginning of the period stay on for an amount
of time determined by their duty cycle, then turn off for the remainder of the period.
After that, this process repeats.
In summary, if a timer is configured to count up, its PWM signals are edge-aligned, and
more specifically, left-aligned.
We will show the PWM mode 2 output, when CCR is 3.
In mode 2, the output is low, if the counter is less than CCR.
The output is high, if the counter is larger than or equal to CCR.
This mode is also called high-true mode.
Here is the timer output.
As the counter increases sequentially from 0 to 6, the output is low initially.
When the counter has reached 3, the output becomes high.
This process repeats.
The duty cycle of the output can be calculated in this way.
In this example, the duty cycle is 4 over 7.
The PWM period equals 7 times the clock period.
When multiple PWM signals are generated by the same timer in mode 2, all falling edges
occur at the same time.
That is why mode 2 is edge-aligned.
This example shows the PWM output when CCR is 3 and 5.
All falling edges of the PWM signals are aligned with the overflow events.
More specifically, the PWM outputs are right edge aligned, because all pulses are aligned
to the right side of the PWM period.
If the timer repeatedly performs bi-directional counting, center-aligned PWM signals will
be generated.
The counter counts up, and then counts down.
When CCR is 3, this shows the center-aligned PWM output in mode 2.
The duty cycle of the PWM output signal is 0.5.
The period of the PWM signal equals, 12 times the period of the input clock.
I will explain why it is called center-aligned in the next slide.
When a timer generates multiple PWM signals, the centers of the PWM pulses are aligned
with the peak value of the timer counter.
In other words, the active pulse of all output channels are placed at the center of each
PWM period.
Center-aligned PWM signals are often used in electronic circuits, such as motor control
and power supplies.
The signals are symmetrical and thus have less harmonics.
It helps reduce noise interference and power consumption.
Software can program the polarity of PWM signals.
Each timer has two PWM modes: mode 1 and mode 2.
These two modes are complementary to each other.
However, software can select the output polarity by writing the CCxP bit in the CCER register.
Software can select either active high or active low.
If it is active high, the output is high voltage for the active state, and low voltage for
the inactive state.
On the other hand, for active low, the output is low voltage for the active state, and high
voltage for the inactive state.
The auto-reload register (ARR) can be updated synchronously or asynchronously.
If the ARPE bit in the timer CR1 register is 1, ARR will be updated synchronously.
An update to ARR will be buffered in a register, named the preload register.
The contents of the preload register are transferred into ARR, when the next update event occurs.
This update mechanism is synchronous to timer's input clock, and timer's output period.
It prevents software from updating the output frequency or period, when the timer is still
performing comparison operations.
On the other hand, if the auto-reload preload enable bit (ARPE) is 0, any updates to ARR
will immediately take effect.
This update mechanism is asynchronous, because the update does not take the clock timing
information into considerations.
Update events (UEV) are generated with respect to the counter overflows and underflows, if
the update disable bit (UDIS) equals 0 in the timer CR1 register.
If the UDIS bit is 1, generation of update events is disabled.
In addition, update events are only generated when the repetition counter has reached zero.
Specifically, when the repetition counter is zero, an update event is generated for
each overflow or underflow.
Let's take a look at how update events (UEV) are generated when the repetition counter
register (RCR) is one.
In the up-counting mode, an update event is generated with respect to every other overflow.
Similarly, in the down-counting mode, an update event is generated every other underflow.
In the center aligned mode, the generation of update events is slightly more complicated.
An update event can occur either on the overflow or on the underflow.
It depends on when RCR was written and when the counter was launched.
If RCR was written before launching the counter, update events always happen on the overflows.
If RCR was written after launching the counter, update events always take place on the underflows.
This shows the generation of update events when the repetition counter register (RCR)
is two.
An update event is generated each third overflow or underflow event.
When RCR is three, an update event is generated each fourth overflow or underflow event.
If the clock of a timer is re-synchronized, the counting of repetition restarts immediately
after the re-synchronization.
When we cascade multiple timers, in a master and slave configuration.
We need a special synchronization operation to start multiple timers simultaneously.
This synchronization process can compensate the signal link delay, and allows all timers
to start simultaneously with cycle accuracy.
However, if synchronization take places, an update event is generated immediately, and
the repetition counting process restarts.
The output of a timer is enabled by a combination of the following control bits: MOE (Main output
enable bit), OSSI (Off-state selection for Idle mode), OSSR (Off-state selection for
Run mode), CCxE (Enable of capture/compare output for channel x), and, CCxNE (Enable
of capture/compare complementary output for channel x).
These control bits are located in the timer register CCER, and register BDTR.
For example, in order to enable the output (OC) for channel x, we need to set the MOE
bit to 1 in register BDTR.
Based on the need of software application, we can choose one of these three configurations.
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