Hi, I'm Mehrmah.
In this video, I'll go over the different tools
you should use to optimize your designs for FPGAs.
FPGAs have a unique reconfigurable architecture
that allows you to run your design with low latency
and high throughput.
To obtain the full benefits of using an FPGA to accelerate
your algorithm, you will need to optimize your DPC++ code
for your targeted FPGA platform.
At this file location, users will
be able to get an initial view of their design's performance
via the HTML report.
Remember to do most of your design and optimization
work based on this report before going through the hardware
compilation stage.
Once you've iterated on your design
and met latency and throughput goals,
you can then carry out the final system-level optimizations
with Intel Vtune profiler.
Let's begin by going over the various HTML
reports that can be used for analysis before compilation.
These reports can be generated and opened with the Eclipse IDE
or generated via the command line
and opened in the browser of your choice.
As you can see, there are four categories
of reports that you can click through.
The Summary tab gives you an overview
of the results of your design, including
a summary of each function executed on the accelerator
device.
This is also called the kernel.
You can also see a summary of the estimated resources
that each kernel uses.
The first thing you should check for
is to see if you've compiled to the right port.
Next, make sure to view the RAM and DSP usage
and that you don't exceed the chip resources.
The Throughput tab contains reports
that show you your design's loop and F Max analyses.
Writing optimized loops is imperative to get the highest
performance possible from your FPGA.
The loop analysis report shows you
how well pipelined the various loops in your design are.
Here, the concept of initiation interval, or II, is important.
II is the number of clock cycles between the start
time of consecutive loops, and having an II of 1
means that every clock cycle is producing an output.
This, ultimately, translates to higher throughput.
To get high throughput, you want your innermost loops
to have an II 1 to make sure that they are not
stalling the outer loops.
If your inner loops are not 1, please read the minimize loop
carry dependency section of the Intel oneAPI FPGA optimization
guide.
After the loop analysis report, you
can view the F Max II report that shows you your design's
scheduled F Max.
This tells you whether the compiler still
predicts if you'll achieve your target F Max.
If you see any of the scheduled F Maxes being highlighted
in red, that means there is a performance
bottleneck in that block.
And here, you have the opportunity
to make tradeoffs on area utilization for higher
throughput.
Next, we have the Area Analysis tab.
This report gives you insight on the area utilization
with more granularity compared to the summary view.
Static partition is dependent on the underlying board support
package, but kernel system is dependent on your code
and shows resource utilization of different arrays.
Here, you can contemplate how to change
utilization of scarce resources, such as RAM or DSP blocks.
The final report's category is the system viewer reports.
This contains the graph viewer and the kernel memory viewer.
These reports are useful when you
want to see how data is being transferred
between the various types of memory of your system
by the different components of your kernel code.
After the compilation stage, you can
utilize Intel Vtune profiler to analyze the performance
of your design at runtime.
This will allow you to view a graphical representation
of the kernel program execution as well as details
on memory and pipe axises.
Once you familiarize yourself with the various reports,
the DPC++ compiler gives users flags, pragmas,
and attributes to control the behavior of specific parts
of your design.
Like with any hardware accelerator,
optimizing for FPGAs requires a certain level
of understanding of the device architecture
in order to get your required performance.
With some investment of your time,
you will be able to quickly harness the power of FPGAs.
To learn more about optimizing, please read the optimization
guide or sign up for an optimization class in the link
provided.
Thanks for watching.