So, so let me go over the device that we're working on.
We call it the deeply depleted channel or
the DDC transistor, and what we've essentially done
is we've, we've taken this, we've taken this
standard bulk planar transistor and thinking here is.
You know, well why change it if you don't have to?
If you can get
like advantages from a bulk planar device, it's going to be
a hell of a lot cheaper, you can lower the voltage.
So, you can control the variation a lot better, it's going to be a better device.
So, what we do is we do channel engineering.
So, we take out the dose from the channel,
you can see that in region number one over there.
And, then what we do is we put in two very discrete planes of
charge, the, the layer number, the layer number two is what we call our
VT setting layer.
And again, like as I said, you need multiple VTs
in order to be a good low power SSE technology.
And, by changing the dose.
In those layers. You know, if you think about it
[UNKNOWN]
is 3D, so it's like I'm sitting at a table
with tablecloth and if I pull up the middle of
the tablecloth, I don't just have the tablecloth go up
in this direction, it comes up on the whole table.
So I don't need the halo source between the source and the drain.
Now I can put the dose underneath and it still applies a potential above it, right.
So that's how I'm able to change the potential in the
channel and then the third layer over there is the screening region.
And what this does is
it terminates the depletion depth, but because it's so hard
dosed, it actually keeps the depletion depth constant across the channel.
So if I'm keeping the depletion dip constant across
the channel, that means my VT is going to be constant.
Which means that I'm going to have much less VT vari, variation.
So basically the, the ability to, you know-, we looked at the prob-,
we looked at the problem, we said okay, we need it to be depleted.
So we need a way to terminate the
depletion, but we also need a way to change
the VTs.
And this is the structure we basically came up with.
Now another advantage to having region number
three because we've got this reservoir of dolls.
Is our body coefficient is very strong, okay now if you go
back ten years body coefficient was actually quite actively used in designs.
you can use it to you know, either speed up the
device, or you can use it to save up on leakage.
However, it's kind of, went out
of fashion, and it went out of fashion,
because, if you look at buddy coefficients for
[UNKNOWN]
as they've scaled, they went away.
Because as your short-term effects increase,
you're done having body control anymore.
As it turns out, you can imagine from the
architecture, there is no body control, because
You can't really get that potential, you know
we got this little opening at the bottom, you can't get the potential into the fin.
So, this is the structure we're basically working on,
and the whole idea behind, behind this is the last
line on this slide which is you know, similar
benefits to FenFit but in, you know, good old fashioned,
[UNKNOWN]
CMOS.
So, here are some silicon results which we have.
And what I have over here is I have this is from a, from a SRAM.
And what happens is because, you remember, I said
because you're depleted you get a performance boost, right?
I, so what happens is we're able to
run our transistors at 0.9 volts instead of 1.2.
This is 65 millimeter technology.
we're able to run it at 0.9 instead of 1.2 and have the same
performance so we get a 50% here at c b squared
if so we get a 50% power savings from our technology.
And the other thing you can see here what I'm plotting
is just that the scatter plot of the different VTs within the
[UNKNOWN]
and you can see how much tocture/
distribution is and that's kind of summarized.
over here where we plucked the SRAM mismatch and you can see
that we're about 40% better on PMOS and about 60% better on NMOS.
And that's a huge amount. I mean, usually if you go into
if you got to a
they'll tell you can lower out sigma VT by 15%.
We can hear
That's a big problem that they have. They can't hit the
[INAUDIBLE].
So 40 and 60% is a very sizable number.
I'm not going to go, go over this. This is not too interesting but this is
actually the very interesting. So, what I have plot, plot over here, the
[INAUDIBLE]
logs in both plots is calculations.
And I wish I could talk, told you this was done on a
supercomputer but this was actually done on my six year old PC using Excel.
And the shaded lines are actual data.
So what this was is, if you take a
million transistors, okay, I know what the leakage is.
So the leakage exponentially
dependent on VT, right?
It's dependent on my swing and my VT, it's a standard equation.
And I know that my distribution is most probably going to be
a normal distribution, a bell, Gaussian, whatever you want to call it.
And, what happens is, if you do the calculation,
so I've got two different codes, I've got the red
and the green So the green is a sub
volted transistor which, which has 30 millivolts of vt variation.
the red is a standard halo based one which has 60 millivolts.
And that's at 50% savings I was basically showing you.
And what you can see is when we've actually got the da, the
data back it lasts pretty much where the calculation was which is good.
What I have on the right hand side here, is
I've taken these distributions and
I've actually computed the leakage distribution.
So, what the leakage distribution is, my
leakage is exponentially dependent on VTE and sub
[UNKNOWN],
alright?
As slow, so what happens is, even though my distributions are symmetric around
the center ET, I've got an exponential curve here of leakage which does that.
So, what happens is, when I plug the leakage distribution.
You can see that it's the red curve, which is the one with the
you know, wad of VT variation, it shifted and it shifts towards the lower VT's.
So what this is telling you is
that if you've got a million transistors, it's the leaky transistors in the
tail of the distribution which are
actually going to cause most of your leakage.
So this happens all the time, you'll see, you'll see a company go.
Okay, we've got a chip, it's got a billion transistors
on, and the leakage is, you know, whatever, pick a number.
One
per micron, and I know the width of my
transistors, so, this part leakage should be 2 watts.
And, then they go run the thing and they put on a
tester and it comes back at 5 watts or something like that.
The reason is, this is the reason.
And it's because it's these transistors over here, in
the tail that will screw you on the leakage.
Now the other thing is, these transistors over here are slow,
now when you designing, now when you designing as a CPU.
Like Intel, they do
[INAUDIBLE]
right?
So, this transistor over here is your 2000
dollar pentium pro, kick ass whatever it's called.
And this one over here is the 50 buck porter, okay?
It's the same design, it's the same piece of Silicon.
It's just we're goes in the distribution.
But if you're in the ASIC market, which is a huge market, right?
There is no
[UNKNOWN].
There's either pauses, or it doesn't pause.
Okay?
So what happens is, in the ASIC market, your
leakage is set by this part of the tail.
And your performance criteria are set by this part of the tail.
So basically only everything in between parses.
So the more, the water distribution actually I've got a slide on this.
This is to help on stuff I want you guys to, I'm going to skip and come back.
This is to help on stuff I want, I want you guys to basically understand.
If
I'm a processor, again remember this, yield equals profit.
Yield equals money, okay.
It's not a science experiment, it's a business.
So what happens is, if I'm in that distribution,
I need the stuff in the middle, I can tell.
The stuff over here runs too hot.
And the stuff over here runs too slow.
So by talking up the distribution I can sell more parts.
Furthermore, if I use a body bias. On the
part that are too slow, I can forward bias it and
then make them yieldable and just fuse it out at sort.
And the same thing for the reverse body bias.
So the thing is, variation and variability is not
just something that's oh, it's a, it's a pain.
We'll, we'll work around it.
It has real financial effects at the end of the day.
And it has to be controlled.
Not only does it affect your leakage, but it does affect your yield.
And it's becoming more and more hard.
It's becoming more and more difficult to achieve high yields at the advanced nodes.
Okay, so this is basically coming back to, I
am not sure if you guys have ever seen these.
These are called butterfly curves. This is how the
drives SRAM.
The basic take away here is that in order
to detect the state you have to have any eye.
In the butterfly curve.
So you can see for the control, 65 nanometer technology.
And these are all measurements, it's not simulation.
You can see that the eye basically breaks down between eh, call it 0.7-ish okay.
And our eye is still pretty much visible at about 0.4.
At about 0.3 it's gone, but at 0.4 it's there.
So why's this important?
Well, when you look at designers, they design at about 20%
[UNKNOWN]
they'll design in 20% margin for their Vmin.
So that means that if they want to run a chip at one volt, the Vmin has to be 0.8.
And if the Vmin is 0.9, well, guess what,
they're going to turn their voltage up to one point one.
Okay.
So this is very important in order to scale
the voltage of a device and to lower power.
Okay.
So the other thing is, and this is again, what you guys should
basically think about when you're doing your projects is how do I get tricky.
How do I take a technology and basically go, Im
going to use this in a different way than people have
actually thought and this is what this graph is so
what we basically did is we took one of our transistors.
And we
the thing and we some phibilation and actually I
do believe we do have Data which corroborates this now.
And nextly, what you can do if you have a technology that has
a low variation is it gives you the ability to change the voltage.
Now I'm not saying you can go from one volt
to 0.5 volts or 0.6 volts and have the same performance.
But not everything needs to have the performance of an Intel CPU.
Okay.
There's a lot of parts
out there especially in the mobile world where I would rather have
the thing as a city be 20% smaller but work for three days.
And, if you're able to control the variation that
is exactly what you will be able to do.
On the other side if you have a good body wash you can
you can go into what's called turbo, you can go into turbo modes.
because turbo mode's, if you changing, the the inversion capacitance.
Well the depletions are in with a back bias.
Your not really,
there's no integrity issues with the gate oxide, right?
So, what happens is using these two things I can basically
load I can go I'm going to reduce my VDD to point six.
I'm going to save, I'm going to be running at one sixth of the power.
And my performance is going to be about 50% less.
Okay. In my case, that's not for me.
But there's a lot of parts over there were that's a good trade off.
And you can't do that with all technologies
because you have to have very good VT variation.
And in the other one where you need a very good
back buys is to, is basically to, is is a turbo mode.
So what you can do over here is, you can basically
get, whatever you want to define this 10-20% percent improvement in performance.
You do take a leakage at of course, but that's for instance if you're,
you know, you got a cell phone and 99%
of the time it's sitting in your pocket doing nothing.
But the 1% of the time you take it
out and you want to play angry birds, that's turbo mode.
Because if it's always on turbo mode, by the time you
take it out your pocket there's going to be no battery left.
Okay? So
[UNKNOWN]
we think it provides finFET-like Enhancements we think the
and the SCE are good very good, very
We think it's a very good device for SoC.
We're not looking at the, you know, the CPU market.
I think the FinFET
[UNKNOWN].
They've got that covered. and then we
[INAUDIBLE].
Because we haven't really changed the fundamental design of the transistor.
Which means that all the IP line of, you know, all
the IP in the libraries that are out there can be reused.
And you must remember that, right.
You guys are going into the world
where you're going to be process and device engineers.
There's someone on the other side who's basically designing with your part,
and they're spending just as much money and time as you are.
So, I think that's going to be a change that's basically going to
happen in the market is I think you're going to see a lot more interaction.
Between technology people and design people.
Because I think the days of just having that
having that interaction be through a spice model
or process, you know, were basically a dev kit.
I think that's going to break down.
And you're going to have more interaction between the two.
So the question is, are FinFETs going to take over the world?
Quite simply, no. Not any time soon.
Okay, I think you guys would be surprised if
you pull a, you're going to search on the
web for the iPhone breakdown, or whatever it is
these, there's all these guys that post the breakdown
of all different parts. You'll be surprised.
You probably, you know, can take the latest piece of technology you bought, I
guarantee you that more than half the parts in there are bought on older nodes.
More than half.
Actually, guaranteed more than half.
Some of the most important chips in your cell phone are bought at 130 and 180.
Okay?
So, if you've got an offer, there's a
company called dialog, alright, and what Dialog does
is they make what's called their PMIX, it's Power management Integrated circuit.
Now, the PMIX, what, y'know, you've got a 3.2 volt battery, right?
But your CPU works at 1 volt, your screen
works at 5 volts, you want the thing to power
down, but still check your email every so often,
that's what the PMIC does, it's one of the most.
One of the most expensive chips behind these, behind the CP
is like 3 or 4 bucks which you go, 3 or 4
bucks, that's nothing.
It's, if you look at all the chips in there, the chips
are $0.20 so 3 or 4 bucks is a lot of money.
And those chips are built on 130 and 180.
Okay, and they don't, okay, they also not
balled completely on CMOS, there balled on BCD processors.
But that's not going away any time, time, time soon.
Same thing with WiFi and Bluetooth.
Think about Bluetooth, right?
At one stage when bluetooth first came out it was 10 bucks for a
Bluetooth chip. Bluetooth is free now.
You ask me how much Bluetooth costs, it's free.
It's just expected that you get a car, you're going to have Bluetooth, you get
a PC, it's going to have bluetooth, you get a phone, it's going to have bluetooth.
It's incorporated, it's
on an SSE nobody cares anymore, alright.
So, if it's working at 64, and you've got something with
all your radios at 65, it's going to stay there, there's no
[UNKNOWN]
to basically move ahead.
So, basically in the next four or five, five years
I think this is going to, got research up in Portland.
I think they're correct, I think what you're going to see at the
advanced nodes are going to be the high-speed GPUs, are the high-speed CPUs.
And all, and, and the very advanced APUs
like the Snapdragons and the, you know, Nvidia Tegra.
But for most of everything else, it's going to,
it's not going to rush there. It really isn't going to rush here.
So the phone you buy in five years time,
still going to have 130 and 180 millimeter technology in it.
Basically let's never underestimate the staying power of technology and
really what that comes down, down to is this slide here.
Which is the industry doomed?
I've kind of set you and told you oh there's no more scaling.
The
[INAUDIBLE]
is done the
[INAUDIBLE]
is done.
The truth of the matter is it's not going to
stop, okay and there's a lot of challenges lying ahead.
There's more challenges lying ahead today for
the industry than there were ten years ago.
And if you have a look at the semi conductive industry now, so I'm including.
Everything that goes onto silicon here, alright?
DRAM, SRAM, logic uh,n
[INAUDIBLE],
whatever the case may be.
It's a $300,000,000,000 market and it's growing.
Okay.
Even though PC sales have slumped a little,
there's other, the analog market's exploding right now, right?
Because we're, we're, craving interaction with the digital world, right?
And when you, when you interact with the digital world it's always Through m log.
So the market's going to grow but more if you look at the total ecosystem around
[UNKNOWN],
there might be 300 billion and I don't know this number.
I just pulled this number out of thin air
but 300 billion is the correct number by the way.
But the other number is, I wouldn't be surprised if
the ecosystem around semi conductors is well above a trillion dollars.
Okay, software.
mobile phones. You know, Sprint.
All these companies, they all, you know, these companies.
You wouldn't have the Android if you didn't have, you know, little
handsets. Okay.
you know, you wouldn't have cell companies rolling out LPE and you know.
If you didn't have the ability to have a phone that
could handle three megabits per second, or six megabits per second.
You know, it wasn't too far long ago that I remember my dad brought home a
28K modem, you know, and I had the 14K, and I was like, dude, this is outstanding.
And I, and the truth of the matter as technology goes
up, our demand for it goes up. So it's not going to go away.
The question is.
What's it going to be?
I don't know what's going to be in 10
years but there's tons of challenges out there.
And one thing I will, I do believe and I do believe we
are actually already seeing it now, is the you know, so called two-year cycle.
Every two years, there's a new technology node.
I think that's going to slow down.
I think you've already seen that slow down.
Intel was about six to nine months late with their FinFET.
It's not a knock on them. I mean, I know.
I left Inel uin the mid.
You know you, you, midway through the FinFET
development, and it, it, they did extremely well.
But even though they did that and they increased the capacs and they put
more engineers on it, it's becoming much
much harder to basically do these technologies.
So I think you might see changes in that, you know, the
two year cycle is definitely, I think, going to become a three,
four, five, five year cycle. And then, my personal thought on this.
I haven't heard anyone say this.
But I think you gotta move to an incremental top market where
instead of going, you know, I'm going to use, you know, 28 nanometers.
Two years from now, it's going to be 29 nanometers.
I think you're going to start seeings guys do incremental changes, you know,
where it's going to be, you know what, we're going to stand 28 nanometers.
And we're going to re release it with the
new design kit where this ten percent performance increase,
you know, and something like that.
So, I think you're going to start seeing things like that.
But, basically, there's, what the market needs
now is more smart engineers, like you guys.
And it's actually a good time to be in the semiconductor industry, because.
As I said, there's so many challenges ahead that you know, it,
it's very tough to get a lot of high, high quality new
engineers who were interested in this stuff.
So, I think you guys have got a bright future ahead of you, and
it, it's going to be different from what you've read about in the last 20 years.
But, it's going to be a good one.
And that's it. Any questions?
[NOISE]