Welcome back to the oneAPI channel.​
I’m writing code, and my performance bottleneck is a specific function,​
It is pretty easy with SYCL, and oneAPI DPC++ compiler
to just take that piece of code and offload it to a GPU for example, ​
yes the same C++ code​
Take a look at the relevant videos on SYCL and DPC++​
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But I have here some custom logic, I do want to offload it from the CPU, ​
but I do not want a GPU, or the GPU does not support well such specific operations​
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How about we just take that specific piece of code and offload it to an FPGA.​
And get all the benefits FPGA has to offer, like on-chip memory , low latency IO and more.​
You do not need to know RTL or be an FPGA expert..​
Let me tell you about the FPGA Add-on for oneAPI Base Toolkit
In previous videos we have talked about the oneAPI components.
We mentioned the multi-device multi-vendor open spec libraries..
That can now work on multiple devices, CPU, GPU and others, what we call XPUs..
And are packed into toolkits..​
For example, the Intel oneAPI Base Toolkit.
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You can start developing for FPGA with the Base toolkit,​
There are lots of materials online, we have a video dedicated to the base toolkit​
and I’ll leave you the link at the end of this video..
First step is to write your code, and make sure it is functional, ​
You can verify that by running this code on the CPU..
Once you are happy with the functionality of the code,
we can run multiple FPGA optimization reports ​
To understand the expected frequency, the performance bottlenecks,
the FPGA area utilization and more ​
You can repeat stage 1 and re-arrange, or re-write the code, until you are happy with the reports.​
All of this could be done using the Base toolkit, on a CPU machine in minutes
Once you are happy with the reports it’s time to compile the code and generate FPGA bitstream​
For this you will need to install the FPGA add-on​
And this process can take many hours.. You can also run it on the intel devcloud..
And finally we can run the code on the FPGA hardware, your HW or on the intel devcloud system​
A great capability here is that you can use Vtune for profiling the data exchange
between CPU and FPGA, ​
For profiling the FPGA global memory and pipes performance and more. ​
So you can understand and fix performance
issues that cannot be spotted by the static analysis reports of stage 2​
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Let’s see it all happening using a simple example..
I’m using a Jupyter notebook example,​
We are using SYCL and the Intel FPGA extensions​
And the actual code we want to offload is here​
You can see the loops, it’s basically a Hough transform​
The only difference is that this code, this kernel, will be submitted to run on a device Q.​
And this device Q, is being selected by the device-selector​
Which will choose the FPGA emulator that comes with the base toolkit​
Or, if it does not exist, the host , our CPU​
File is here and I am compiling it on the Intel devcloud for the FPGA emulator.
​ The device code,
the code that will eventually be run on the FPGA need special treatment​
This is the code that we need to optimize
so the FPGA will provide our required power/performance targets​
This is the code that we’ll use to create the bitsream from, ​
handling the host code is easier and faster​
So it make sense sometime split that code into a separate file,
check out the documentation on how to do it
And I’m basically compiling the code, I got here 2 C++ code files,
the main for the host and the kernel for the FPGA​
And I’m generating the reports
​For the reports, you have to understand something about FPGA
and programming for FPGA.​
For example, this is the loops analysis, you choose a loop, you can see the actual code​
And the cycles between each loop iteration, this one for example has to be fixed​
System view , the control flow and the corresponding code​
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Area analysis​
This static partition is here to operate the host-device interaction and execution​
And it takes about 20% of the area​
The actual kernel code is consuming only 1 to 5%
of each of the areas categories, it’s a small logic, ​
And the summary report will give you the bottom line
of the expected clock frequency, resources utilization and more..​
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Base on these reports we can go back and improve the code using a full set of techniques​
Like Banking, loop unrolling, using local memory vs global one and more​
you’ll find many such examples in our oneAPI samples and documentation
And now we can generate the bitstream,​
We need the specific version of the FPGA add-on to match our hardware,
And running the application, here I’m using a FPGA system in the intel devcloud,
but you can of course do it locally
So, the easiest way I’m aware of, to write custom code and offload it to an FPGA​
Use the base toolkit for code verification on an FPGA emulator and generate optimization reports​
Use the FPGA add-on to generate bitstream to your FPGA​
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Enjoy, subscribe​
Thank you