Hello.
This is Ray from MathWorks.
In this video, I'll introduce you
to the Linear System solver and the Matrix Factorization blocks
in the Fixed-Point Designer Toolbox.
This set of blocks can solve linear systems,
such as a times x equals 2b, and a transpose a times x
equals 2b.
So [INAUDIBLE] are commonly used in beamforming applications,
like radar, wireless communications,
and audio applications.
All these blocks are built based on hardware-efficient partic
algorithms.
They are also compatible with HDL Code Generation workflow,
so they can provide a user fit and cycle accurate simulations,
as well as generate efficient HDL code for FPGA or ASIC
deployments.
On the application side, we also have an example
shows how to implement a fixed-point HDL-optimized MVDR
Beamformer.
In Matlab 2022b, several new features
are added and improved for this box.
And let me walk you through them.
The first improvement that we have in this object
is the latency of complex partial systolic QR
and the [INAUDIBLE] blocks are reduced by about 50%.
This is achieved purely by pipeline optimization,
so the accuracy of numerical calculation remains same,
and no additional hardware resources
are required in the generated hardware design.
Here is an example shows a direct comparison
between a 22a model and a 22b model.
We run the model, and notice that the data we
feed into these two blocks are exactly same,
and we monitor the latency between the value the data
input and the QR become ready again.
Let's open up the Logic Analyzer.
And then, we can see that, in the 22a model,
the latency of this model is about 73 clock cycles,
and in 22b model, this reduced to 38 clock cycles, which
is about two times faster.
This reduction in the latency to help
users to achieve higher throughput as well
as lower cost, since FPGA with lower clock rate can be used.
The second enhancement that we have for this Blockset is we
adopted the AMBA AXI handshaking protocol to all
our QR and matrix solve blocks, the fixed-point designer
toolbox.
And briefly speaking, in this protocol,
the upstream and downstream block
acknowledge the data transaction when
both ready and the valid signal are asserted.
And this example covers the three common use cases,
valid before ready, valid with ready, and ready before valid.
We can run the simulation, bring up the logic analyzer
and zoom into the data transaction part.
So we can see that in the valid before ready case,
the upstream data source block get data prepared before QR
ready to consume it.
So the valid signal is asserted first.
And when downstream ready is also asserted,
both blocks assume the data transaction
is finished and then move on to the next state.
Similarly, in the ready for valid case,
the downstream is ready first and waits for the upstream
to fill in data.
Again, when both ready and valid signals are asserted,
both upstream and downstream blocks
consider the data transaction is done.
The last use case is valid with ready.
This means upstream and downstream have same latency.
So the ready and the valid signal asserted at same time.
And then they move on in the next block.
We believe that the standardized protocol
can help users to interface with our blocks
easier and make the data transaction more robust.
The last new feature we added is a new set
of blocks that support asynchronized [INAUDIBLE]
matrix solver.
This box solves linear system, A transpose A times X
equals to B. If you look under the mask,
so this block consists of two major parts, the Q-less QR
decomposition and forward backward substitution.
In the asynchronized implementation,
the substitution blocks does not wait for the result from QR,
but it runs continuously using the latest buffer data.
This example is viewed based on our complex burst asynchronous
matrix solve block, and that we can run this simulation.
Now let's check the results.
For demonstration purposes, the input A matrix
is toggling between two matrices,
while B matrix remains constant.
We can see that the system generates output
at a constant rate.
And the output value also toggles
between two solutions, which are corresponding to the two A
matrices.
And this asynchronized behavior is
particularly useful for beamforming applications.
In such a system, the data from the sensor or antenna array,
which representing by this A matrix,
usually comes in at a constant rate.
But the steering angle, which represented by B,
is already controlled by other mechanisms at different rate.
So decoupling the matrix factorization
and the substitution allows the data
from sensing elements keeps flowing in without affecting
downstream processing.
And this helps the user to reduce
timing constraints, which in turn lowering
the overall system cost.
We also want to highlight that for all the above
mentioned the blocks, we have two architectures in which
the first implementation is optimized
for smaller footprint.
And the partial systolic implementation
is optimized for high throughput.
In summary, the matrix factorization
and the linear systems solver blocks,
the fixed-point designer toolbox can system
equations A times X equals to B and A transpose A times X
equals to B.
The HDL optimized model can provide a user fit
and cycle-accurate simulation result.
And this box can also generate efficient HDL code
for FPGA and ASIC deployment.
Thank you.