In this tutorial, I will show you the clock configuration on the STM32L4
discovery kit. There are three external clock crystals on the board. This is 8
MHZ crystal connected to the ST-Link, which is used for debugging the L4
processor. And this is 32 KHz low speed external, and this is high-speed external
crystal. Unfortunately, it has not been populated. And there are also three
internal RC oscillators within the processor chip.
LSI (low speed internal), HSI (high speed internal), and MSI (multi-speed internal). Let me show you a software. If you download the STM32CubeMX,
it will show you a nice clock tree diagram to configure the clocks. We have low speed external,
which has been populated on the board. It has 32 KHz. Low-speed internal has been fixed to 32KHz. We have multispeed internal (MSI), and
it runs from 100 KHz, up to 48 MHz. The default clock frequency
of MSI is 4 MHz.
This is high-speed internal (HSI), and it is fixed to 16 MHz.
It has high-speed external (HSE). Compared with internal clocks, external crystals
tend to be more accurate but takes more space.
So, a processor, Cortex core, can be driven by a clock
up to 80 MHz. So we can set the core clock by using four different
clock sources: MSI from here,
HSI from 16 MHz, HSE from high-speed external crystal, and also PLL. PLL can be driven by
MSI, HSI, and HSE. Next, I am going to show you a source code.
How to use the 8MHz MSI to drive the Cortex core. If you go to the book website, and
Here, "example labs", go to "lab description", and go to "Lab 5",
This is Lab 5. Here, system timer. Within the lab 5 handout, there is a clock tree.
I am going to show you the source code. In this source code, I will show you how to select MSI, 8 MHz, to drive as the system clock.
And first of all, in the source code, I turn on the MSI clock, and then I clear SW bits in CFGR register.
Let's take a look at this selection mux. So I want to select MSI as the clock source. So that SW bits in
CFGR register have to be 00. That's why I clear these two bits. And then, I wait until the MSI is ready. The reason is we cannot modify MSI
range in CR register until MSI is ready or MSI is off. So I want to select 8 MHz
and I clear the range first, and then I select MSI_RANGE_7 (0111), which
is 8 MHz. There are two MSI ranges. One is in CSR register. The other
one is in CR register.
Which one is used depends on the MSI range selection bit in the control register. So I select CR
by setting the selection bit to zero. Then, I wait until MSI is ready again. In the next example, I am going to follow the red lines shown in this clock tree to select
16 MHz HSI as the clock source, and then use it to achieve the max frequency supported by the core, which is 80 MHz.
The idea is like this. We use HSI, and then by setting the PLL source register, seting these two bits to 10.
So this is 16 MHz, then we set the factor PLLM as two, divided a factor of M. So we get 8 MHz.
We have 8 MHz coming to the PLL. We multiply it by a factor N. We set N to 20.
So 20 times 8. We get 160 MHz.
And then we set the factor R to 2. So 160 MHz divided by 2, which is 80 MHz. So we use this 80 MHz. And then here,
the source selection bit in the CFGR, we select 11. Make sure we set these two bits to 11. Then we use this 80 MHz to drive the system clock.
There is one minor change (error) in the clock tree diagram. The system timer clock should be /1, 8.
So it is either divided by 1 or divided by 8. The diagram only shows divided by 8.
So Let's take a look at the source code.
Here is the source code to select HSI, 16 MHz,
and follow the red tree, red lines to set the system clock as 80 MHz.
So one thing we need to pay attention is that when we use 80 MHz, Because the flash memory is not fast enough,
so that's why we need to add some latency here.
If we don't add these two lines of code, then we will not be able to reliably read data out from the flash memory. I have spent huge amount of time to find out the error I had.
So, let's turn on HSI, and wait until HSI is ready. And we have made some adjustment. HSI has some internal adjustment.
Factor is the trim parameters, being stored on the chip by the manufacturer.
And then we turn on the PLL here.
and the we select the clock source, and PLL clock source has to be HSI in this example.
There are three clock sources: MSI, HSI, and HSE. We select HSI. So we get 10, get 8 MHz.
And then we set all different factors here. We set factor N,
factor R, and factor M here. So we get 80 MHz.
After that, we enable PLL clock. And we turn on PLL clock, and we wait until PLL is ready. After the PLL is ready, we select
this one. Basically, it is this one. We select the PLL clock as the source for the system clock. Then we get 80 MHz.
And at the end, we wait until
the system clock has been successfully selected.
By this time, we should be able to have a 80 MHz clock to drive the core.