CMOS Technology: NMOS and PMOS Transistors and the CMOS Inverter
Let's start with the MOS transistor.
Here we see an enlarged cross-section view.
The letters M-O-S refer to the structure of the transistor: a metal gate, a thin oxide
insulator, and a semiconductor channel.
Another name for this device is insulated-gate field effect transistor, or IGFET, or MOS
Field Effect Transistor, MOSFET.
This particular transistor is the NMOS type, or N-channel, MOS transistor.
It is fabricated in a P-type silicon substrate and has an N-type source, N-type drain, and
gate.
In the early days, the gate was made of metal, but now it is made of conducting polycrystalline
silicon, or "poly" for short.
The gate rests on a very thin layer of silicon dioxide, which is the clear mineral quartz,
an insulator.
Beneath this is the transistor channel, which either conducts or does not conduct electricity
between the source and drain, depending on the voltage applied to the gate.
There are metal connections to the substrate, source, gate, and drain.
The substrate and the source terminal are both held at the ground voltage, 0 volts.
When you apply 0 volts to the gate, the source and drain remain isolated.
The drain is not connected to anything electrically, so we say that it is floating.
There's basically nothing going on here.
On the other hand, if you apply 1 volt to the gate, something interesting happens in
the channel.
The positive voltage repels and pushes away the mobile, positively charged holes, leaving
behind immobile, negatively charged acceptor atoms in the P-type silicon.
This creates an electric field between the gate and the channel, which effectively changes
the P-type silicon to N-type, and creates a conducting channel between the source and
drain.
The region of temporary N-type silicon in the channel is called an inversion layer because
it is "inverted" from P-type to N-type silicon.
The transistor works like an on-off switch.
When you apply 0 volts to the gate, the source and drain are disconnected and the switch
is off.
When you apply 1 volt to the gate, the source and drain are connected and the switch is
on.
Now let's look at the PMOS transistor.
It is fabricated in an N-type silicon substrate and has a P-type source, P-type drain, and
poly gate.
There are metal connections to the substrate, source, gate, and drain.
The substrate and the source terminal are at held at the supply voltage, 1 volt in this
example.
When you apply 1 volt to the gate, the source and drain remain isolated.
The drain is not connected to anything electrically, so it's floating.
However, if you apply 0 volts to the gate, which is negative compared to the substrate,
it repels and pushes away the mobile, negatively charged electrons in the channel, leaving
behind immobile, positively charged donor atoms in the N-type silicon.
This creates a P-type inversion layer that provides a conducting channel between the
source and drain.
The effects are the same as for the NMOS transistor, but with opposite voltages and silicon types.
Again, the transistor works like an on-off switch.
When you apply 1 volt to the gate, the switch is off.
When you apply 0 volts to the gate, the switch is on.
Now let's look at CMOS, or Complementary MOS technology.
Both NMOS and PMOS transistors are fabricated on the same silicon chip.
The PMOS transistor is made inside an N-type silicon region called an N-well.
The P-type substrate is held at the ground voltage, 0 volts, whereas the N-well is held
at the supply voltage, 1 volt in this example.
This P-N junction is a reverse-biased diode, so no current flows from this N region to
this P region, in spite of the voltage difference.
The N-well is effectively isolated from the P-type substrate.
To create an inverter, first connect the source terminals to the respective power and ground
supplies.
Next, connect the PMOS and NMOS gates.
Finally, connect the PMOS and NMOS drain terminals.
The node connecting the gates is the input, and the node connecting the drains is the
output.
When the input is 0, it turns on the PMOS transistor and turns off the NMOS transistor.
A conducting path through the PMOS channel carries the 1-volt supply to the output.
The NMOS drain is isolated from the NMOS source.
Conversely, when the input is 1, it turns off the PMOS transistor and turns on the NMOS
transistor.
A conducting path connects 0 volts to the output.
The PMOS drain is isolated from the PMOS source.
To summarize, when the input is 0, the PMOS transistor is on, and the output is 1.
When the input is 1, the NMOS transistor is on, and the output is 0.
This is the inverter logic function.
Now let's take a look at the chip layout for the inverter.
There are various ways to lay out the transistors and connections.
Here's one example.
This is the view looking straight down toward the chip surface.
The mask layer for each material is shown in a different color.
This is the PMOS transistor channel, with the poly gate shown in red, and the P-type
source and drain on two sides.
Similarly, here is the NMOS transistor.
The two transistor gates are connected to the input node, and the two transistor drains
are connected to the output node.
The N-well and PMOS source node are connected to the 1-volt supply voltage.
The P-type substrate and NMOS source node are connected to ground.
The X-boxes are the contacts, or vertical cuts, through which the metal makes connections
to the silicon.
You might wonder why the PMOS transistor is larger than the NMOS transistor.
The PMOS transistor is intrinsically weaker per unit area, so it must be made larger to
balance the electrical characteristics of the NMOS transistor.
The next video shows a live demonstration of an inverter gate model using ordinary household
light switches.