My father was a chip designer. I remember barging into his office as a kid and seeing
the tables and walls covered in intricate diagrams and drawings. I watched him work
in fascination as he painstakingly drew lines I did not understand.
These days, nobody draws circuits anymore by hand. In this video, we are going to dive into
a critical software tool for chip designers - Electronic Design Automation or EDA.
Without this unheralded software, many of today's most advanced chips cannot be made.
Before we can understand how EDA software helps the chip designer, we need to know
the chip design process flow. How does a company like Apple or Nvidia design their custom chips?
The process (and names) differs from company to company.
But a generic flow might look something like this.
First, the product designers and system engineers at a high level envision a product.
They might not know much about circuit design, but they do know what their customers want. And
so they come up with a set of integrated circuit requirements based on the customer’s needs.
Next, the chip's requirements enter logic design (also called circuit design). These people
translate abstract requirements into circuits with the logic capable of meeting those requirements.
Think of it like a UX designer who crafts how a software feature might look,
act, and feel together with a product manager.
A chip has many circuits on it and those circuits do different things.
I’ll briefly touch on two such circuits.
Logic circuits, or gates, act sort of like a decision box. It receives inputs,
puts them together, and comes out with an output.
Is A equal to B? D is TRUE only when E and F are also TRUE. Stuff like that.
Just one logic circuit by itself can seem pretty simple,
but in groups they can do amazing things. Like zombies.
The second type circuit is a memory circuit. It is capable of remembering
whether a value was true or false. Kind of like a light switch that is on or off.
Once the logic designer has completed their work, they end up with groupings of logic and
memory circuits connected together with wires. This grouping is referred to as a "netlist".
After logic design, the design gets handed over the physical designers.
The work they do involves the literal, physical layout of the logic circuits,
memory circuits, and the wiring between them on the chip.
When you have thousands or even millions of such circuits, this can get difficult.
Once it goes through all of that, the chip design is verified and
tested for errors before being sent to a foundry like TSMC or Samsung Foundry.
EDA software is heavily involved in every one of these stages. Even TSMC as the foundry uses
EDA software to check a newly arrived design to make sure it is compatible with all of
their design rules. Such testing or "Design Rule Checking" is an especially big deal.
An error here can cost millions of dollars if it slips into the fabrication stage.
At the early stages of chip design, basically until the 1970s,
chip designs were done by hand. The designer would draw a design on paper.
This paper design would then be transferred to a photomask made of a material called rubylith.
The photomask can then be used to produce the chip design's patterns
on the substrate. This is done by projecting light through the mask onto the material. So on.
But as chips got increasingly more complex with more transistors and connections,
simple software tools were developed in-house by the big companies to aid in the design
process. These tools would become the EDA software tools used today.
The first software programs automated the placement of a very small number of
blocks and wires on a circuit board. Not the chip, but a circuit board.
Routing makes sense for these early programs because the task gets tedious. It also needed
to be constantly done over and over again as board components moved around. At the beginning,
these big mainframe programs ran simple breadth-first search algorithms across a grid.
Breadth-first, meaning they explore all the possibilities at a single “level”
first before diving deeper to the next “level”. This is rather slow,
so those programs quickly moved to other algorithms in later versions of the software.
As the number of components within an integrated circuit started to exceed
that on a circuit board, EDA software usage moved to the silicon domain.
Bringing EDA to silicon helped solve daunting challenges in chip making.
A chip is built in layers. Now you have to wire connections in 3-D,
taking into consideration layer-to-layer connections called vias.
It adds astounding amounts of complexity and presents huge opportunities for errors.
And would lead to a chip design problem.
Moore's Law - an observation not a real law - set the pace for the semiconductor industry
to produce chips with ever increasing numbers of transistors.
Assuming the industry follows Moore, that translates to roughly
a historical 58% annual rise in the number of transistors that fabs are capable of fabbing.
Being capable of fabbing that many transistors is one thing,
but designing the actual transistors to be fabbed is another matter. Design can only go
along so fast because human knowledge and skills cannot scale up as fast as tools and capital.
If you disagree with that statement then I recommend you check out the
"Mythical Man-Month" or other works on project and software management.
At the same time, consumers and customers want that next hot chip in their hands right now.
What results is a gap in productivity between design and manufacturing capabilities.
A company like AMD might need a few years to come out with a 5nm chip
even if TSMC had the capacity for them to use. Imagine if mega-customers Apple and
Huawei weren’t around. Would TSMC even bother to put out the 5nm process node so quickly?
Better EDA tools are the only practical way that chip design teams can keep up and close that gap.
Commercial automatic physical design systems began emerging in the 1980s. This came as a
result of not just improved computing power, but also powerful new display technologies.
The first EDA software literally just drew things on paper like a printer.
The advent of reasonably priced storage-tube class CRT screens
made the industry much more accessible to industry designers.
The industry also pioneered and adopted new approaches to chip design that unlocked more
of the EDA industry's automation powers. Engineers in universities advocated for a
more space-efficient design style on pencil and paper called programmable logic arrays.
But EDA software for this style did not scale very well.
You had to do a lot of re-drawing whenever components changed.
And conceptually, people had to handle the design at both a high
and low level of abstraction. This made designing difficult.
It is kind of like having to architect a house while crafting the bricks at the same time.
The semiconductor industry on the other hand, developed a "standard cell" style.
Here, designers choose from a library of standardized groups of gates
called "cells" and decide how they are wired together.
This allowed the design process to split into the separate logical and layout functions I
mention today. It abstracted away the bottom level stuff and let people focus on their own areas.
And because the cells are standardized, EDA software can consistently create
electrically and physically correct designs all the time.
Several criticized the style for being less area efficient.
Some early standard cells had half of their area being taken by routing. But because
its EDA worked so much better for designers’ work flow, it became the industry standard.
Think of it like with programming. You can write, test, and debug a program much
faster if you did not have to sit and wait several minutes for your code to compile
every time you made a change to it. Such a programming language is likely
to gain traction even if it isn’t as efficient as other alternatives.
An EDA industry sprouted to service various parts of the chip design process.
Over time, those software firms consolidated as tasks got harder
and required integration across various stages of the design cycle. Their
proprietary libraries would end up being the de facto standard across the entire industry.
The two leading companies in this space
are Cadence and Synopsys. Both are based in the United States and are publicly traded.
Cadence has a $34 billion market capitalization and Synopsys $36 billion.
The two companies are the creation of a long series of acquisitions. They have
been involved in the industry for the long time and have struck alliances with large
players like TSMC and Samsung Foundry to help solve problems in transitioning a
chip from the design to the real world. They just make things so much easier.
For fabless entrants looking to enter into the semiconductor world,
they likely have to go through these EDA vendors and get their software to get started.
Your company might have to pay millions of dollars to acquire a whole bundle of software tools,
a common trick in the SaaS business.
Beyond just the EDA tools, the companies own a lot of IP as well.
They make money licensing out useful IP blocks for standard functions in a chip
like I/O. Kind of like how in Canva, the online graphics design tool that I use to make my videos,
you have to pay $1 for this little flower clip art you want to use in your design.
Sure I can go find something else or even make my own, but why bother? This works the best.
As a result, both companies have very good gross margins and strong cash flows.
Software subscriptions and IP licenses businesses are like that. And so they can spend a whole lot
on R&D to further extend their current advantages. Their positions therefore are pretty rock solid.
Their stock valuations already reflect all of this, in case you are wondering. This stuff
ain't cheap. I would not go out and starting buying these companies’ stocks any time soon.
There are a few companies out there challenging the two major incumbents. Google apparently
made their own EDA tool to design a recent YouTube chip. That is really interesting.
There are a few Chinese alternatives like Empyrean and Cellixsoft that recently
have gotten increased attention due to the US-China trade war.
Not to mention open source EDA tools for things like RISC-V.
Such efforts as of now remain undeveloped and lag the market leaders.
For EDA-enabled chip design, exciting new developments remain on the horizon.
Programmers are applying machine learning to EDA software, showing some promising new results.
For example. ML can help EDA tools find an optimal route for the wires between the chip's circuits.
It can help simulate what sorts of patterns a
photomask design will project during the lithography phase.
Outside of ML, vendors are still experimenting with new techniques to
best adapt to this new industry trend of systems-on-chip or SOC designs.
Without EDA software, the cost of creating new chip designs would soar
even faster than they already are. They are a critical part
in the industry and today’s amazing chips would not exist without them.