This brings us to this important question that so what really happened?
What really happened from 2004 to all the way till 2012.
Of course, the semiconductor industry did not
die, so you know, something must happen.
Right?
So, what I'm showing here are actual
images of a technology generations, different technology
generations and I'm.
Showing the image, actual images of transistors from these different different
technological generations, so 30 nanometer, which was launched in 2010, 45
nanometer 2008 65 nanometer 2006, 90 nanometer 2004.
So, looking at these images, probably we can,
you know, we can get some knowledge of what
actually happened from 2004 to 2010.
So this is an analysis done by Victor Moroz from a
colleague of mine from colleague and friend of mine from Synopsys.
And So what he did was he, Victor what
he did was he carefully plotted all these images.
And on the, on this chart the important thing to note is all
these images have the same scale. So these aren't scaled up or scaled down.
But they have essentially the same, same scale.
So we can compare them over here. And then, what Victor did
was he actually very painstakingly he measured the physical gate length.
So what Victor did was he measured the physical
gate length, that is, the length of the gate from,
From the gate line, from 90 nanometer, to 65 to 45, to all the way to 32 nanometer.
And what he came up with was actually quite surprising that Mr. Denard says
that, you know, keep scaling the gate length by 0.7 x every generation.
But what which was which is stated in the ITRS roadmap.
Also, the ITRS roadmap says that, you know, every technology
innovation from 90 to 32, you should be essentially going
along this chart, which has 0.7x reduction in gate length with every generation
But what Victor found was actually, it was, it was not, happening like that.
What he found was actually, the, the, the gate lengths were only
scaling as 0.9x every, every technological innovation.
So he, that was quite surprising but then maybe, you know,
we think okay, so there in that equation that I described earlier that
your Id is proportional to this W by 2L and
to your Cox and to your VG minus VT squared.
So this this length is actually not, not the, not the physical gate length.
What I mean by that, that you can have a transistor with a very large
gate with a very large gate length, but it's actually
this length that could have a large physical gate length.
but the source and drain could be diffused.
The junctions could be diffused further.
And this, this length in this formula is actually this physical, it's not this
physical gate length but it's it's a, this electrical gate length.
Also known as an L
effective which is essentially half Far is your source drain junction,
from your how far is your source junction from your drain junction.
So, Victor, what he thought was, okay,
they're not scaling the physical gate length, but
maybe they're, you know, they're bringing their,diffusing their
implants further so that your source and drain
come together and probably scaling their effective length
To double you know to make sure that whether it's happening
or not, what Victor further did in his analysis where he
also measured this Not only the physical gate length but he
also measured the, measure how far these junctions were diffusing in.
So you know you can use very sophisticated
techniques such as SIMS to measure how far your implants have diffused
and you can calculate actually your, the shape of your dopants and
you can calculate, you know where exactly your source drain junction.
So, shown here is, is this 90 nanometer node, and it has a
physical gate length of 45 nanometer, and the junction is diffused till here,
and this effective length is actually much less than the physical gate length.
This is actually only 25 nanometer.
But to his surprise, when he measured the same thing in 32
nano-meter node, so this one has a physical gate length of 30 nano-meter.
And he measured these junctions.
How far they are diffusing. So they were defusing much less.
So they,
moving from 90 to 32 people were able to control this diffusion of
junctions even better. And this gate length was actually, you
know quite surprisingly it was not scaled at all it was scaled from
from a three technological generation it went only from 25 to
24 nano-meter. So,Victor plotted his analysis in this
very nice chart. So what he says was your gate length
actually since the last eight years have been scaling as 0.9x, instead
of Mr. Denard's prediction of 0.7x.
The junction actually have been scaling, the junction diffusion has
been scaling quite well, and there have been scaling like 0.7x.
And the physical, I'm sorry not the
physical, the electrical gate length, which is the separation
between your source and the drain junction, that has not scaled at all.
So this has pretty much stayed around 25 nanometer
for, you know, for for four technological generation now.
And Victor probably you know, he said that the sweet
spot of gate, electrical gate length you want to operate it.
And a lot of it has to do with the variability and we
will talk about that later if you're, if you keep on reducing this
effective gate length you increase your variability quite a bit and it becomes
very difficult to make make microprocessors
which have billions of these transistors without
without hurting with all of them working.
So, that, that's one of the reasons,
but essentially the main conclusion that I want
to draw is this effective gate length
in our equation for current hasn't been changing.
So, but, but, you know, what
Moore's law was not exactly dead, people were actually printing
more and more transistors in the same die, so the number of transistors was
actually increasing twice, for every technological generation.
So, how is that happening since, you know the
physical gate length
which.
Which essentially determines how many transistors you
can print was actually going as only 0.9x.
So how was the transistor density, your transistor density,
how was its scaling up, or your, how was your actual transistor area, or
How was your actual transistor area for SRAM was going down on your density was going up.
And the reason of that, and how this was being made possible, that instead of
scaling the physical gate length, the physical gate
length was actually just scaling as 0.9 x.
But the contact for your transistor which is how far is your source
and drain from your source and drain plug from your from your gate.
That was scaling much more aggressively, and so
you're actually your pitch was still scaling as a
0.7x because your contact according to this analysis by Victor.
Was becoming more and more closer to your gate.
And this is bad for
as we'll analyze in one of the problem sets.
But essentially it reached a point at 20 nano-meters, 22 nano-meters if you wanted
to continue scaling this In this way there was no space left for contact.
So there was no space left to land your contact.
So this really kick started this era of non
classical scaling, that is scaling that is not governed by Mr.Denard.
It's, Denard's, law.
But we essentially look for more variables,
or, another means that we can still
use to enhance our transistor performance, or
increase or decrease our, decrease our, circuit delay.
So what Mr. Denard, said was you know scale the width and the length
and, he scaled the oxide thickness, but oxide thickness was
as now as we realize we can't scale it any further.
As a consequence of that, we cannot scale
the voltage anymore, but what about these other terms.
So there is still mobility and this term that I
didn't look into earlier which is the dielectric constant of my gate dielectric.
So can I play with these terms. most of
the you know, improvement in your chip performance has since 2004 has
come from these from these non-classical scaling methods.
So, shown here is, is this chart described by Kelin Kuhn from Intel.
And what she is showing is that, you know,
if If you look from a classical perspective
we didn't really scale the electrical gate that much,
so if you look at the current and actually
from the classical equation you wouldn't get any improvement.
We were still able to improve this current
because we employed all these non classical techniques.
So we employed this technique known as strained silicon, which you.
Used to modify your
mobility of your transistors, and that, you know,
gave us this this much increase in our current.
We also employed this Hi-k-Metal Gate
technology, and that gave us this further
starting from 45 nanometer, and that gave us this further increase in the current.
So since 2004, what has happened is essentially this non-classical scaling.
So which requires
this strained silicon, this High-k Metal
Gate, and more recently a change in the transistor architecture and we will
spend another section talking about these recent developments
and we'll spend another section talking about the Tri-gate or FinFET transistors.