I hope it's obvious to you know, that to enable this heterogeneous integration in
your smart phone or your tablet device to reduce this interconnect length.
Also to reduce your form factor, the only way to do
that is to stack these chips, either on top or side by side.
So there are two ways you could do it. You could either stack, in a 3D
manner which is more, revolutionary approach.
Where you take yours.
So you had a memory chip and you had a logic
chip so you would stack your memory on top of your logic.
And you connect them using this through silicon via
which enable this connection between your memory and your logic.
A more evolutionary approach which is currently in production now is using
This thing called 2.5D or placing these chips on side by side of each other.
And then you use a silicon interposer which is a passive layer.
Essentially what it means is that it doesn't do any processing.
It doesn't add any functionality. It's only purpose is to route
the signal lines between your. Memory, and your memory and
your logic.
So,we use this silicon interposer to route the
signal between our memory and our logic chip.
We also use the silicon interposer, which has through
silicon via, so this silicon interposer has through silicon
vias which which help this overall Package to, connect
it to the PCB to bring the power supply
in, and to connect this overall package to your PCB.
So, the, the more revolutionary approach that
I talked about was essentially going, 3D.
So what it requires is, it requires this through
silicon via through these chips which are all active.
So all of these are active layers this memory and D Ram,
and your micro processor All of these are active layers and whenever you
are enabling this through silicon vias, through your
active chip, a lot of concerns come into picture.
So one of the concerns is obviously each of these steps
will heat up so one of the major concern is thermal management.
Another concern is which stress so this through silicon
via, the process of making this through silicon via.
Produces a lot of inherent stress in the chips so you have to to keep a keep out
zone around through silicon wire to manage
the stress in your chip. The more, so people looked at that, and
they said, gee, this, you know, this looks way too hard, so, let's, let's give
it to the lab guys to play around with it for a few years, and, what they end up,
producing in the meantime was, This thing called 2.5D.
So the, the way this works is you have a
silicon interposer, so you have this silicon layer, which is used
to route all your signals between your between your microprocessor
and your DRAM, and between your DRAM and your NAND flash.
And you could then have these through silicon vias
over here, and then this would be used to connect this
overall overall chip to to, to the package
below to bring in the power supply voltage and route the, all
the signals to your PCB. And so you,
you get around since the silicon interposer is a passive layer.
So you don't have to worry about thermal issue here, you don't have to worry
about stress because you know even if this, this thing heats up,
this this silicon interposer heats up or it has a lot of stress.
It doesn't affect your performance much because
the silicon is esentially a passive layer.
It's not doing any signal processing on its own so all
it's doing it's routing this, routing the connection between your different chips.
So this is something which which was actually
introduced by a company called Xilinx in in, in 2011.
So there are, there are two big announcements
in the semiconductor industry in 2011, one obviously.
Was the FinFET technology introduced by Intel.
The second big announcement was that this this 2.5D technology
or interposer introduced by Xilinx. And.
So, Xilinx is a company which make these FPGA chips or Field
Programmable Gate Arrays and what they did in this chip is they took four
of these FPGA chips, which were made using 28
nanometer technology and they connected them on this single die
using a silicon interposer.
So a zoomed-in view of this is shown over here.
So what they did was they took each of
these FBGA chips, made out of 28 nanometer node technology.
And then you use microbumps to connect it to this through these microbumps to
connect it to this Silcon Interposer, and
the Silcon Interposer was made using different technology.
So since you don't need that fine routing here, they
use a 65 nano-meter technology to make this Silcon Interposer.
And it has four levels of this wiring to connect these FPGA chips.
And then you place them side by side.
Also to bring in the power supply and to
connect it to your PCB, you have these through-silicon Vias.
So you have these through-silicon Vias.
Inside your Silicon Interposer to, bring in your power
supply and, connect your overall package to your PCB.
So, this is, showing another image so you can
see that, you can see this Interposer layer here.
And you can see one of these chips here
and these are connected to the interposer using this micro-bumps.
And you can also spot this TSV through silicon-vias which
are which are essentially connecting this overall die to your PCB.
And Another thing this, this technology allowed Xilinx was
actually achieve reduction in their overall cost.
So why, why, was this? You know, they introduced a new technology
that all, did all this fancy interposer thing.
So why was, why was this cost reduction possible?
So the reason for that is, as you increase your chip size.
So, you have a chip, size of, say, x and you
You want to enable, a memory chip which is four times.
So if you, if you enable.
If you make your chip which is four
times the size of this, your yield actually substantially
goes down.
Instead, if you made, four of these, Chips and you could
connect them using this interposer, you could achieve a much higher yield.
So that's what it's shown here.
They were actually able to achieve a linear increase in the cost with the, with
increase in your memory size and increase in your area of your overall memory capacity.
As compared to if you make it in one single chip, you
would actually in, in, in, in,
actually, you'll achieve exponential increase in cost.
So it, it helps in reducing your cost, as well.
So a question I want to ask you is,
why make this interposer, why make this interposer in silicon?
Why not just use a PCB for making this? So there.
Two options we can have for making this interposer
material, you could either make it, silicon or you could
make it actually in the PCB material itself.
So, one of the reasons that you make it in this in
this silicon is that now you can use of this VLSI technology.
For example in this case, if you used 65 nanometer of VLSI technology,
and using this you could enable a much higher I/O density or you could
place these interconnections very close to each other because
now you are using the VLSI technology available in silicon.
Another reason of doing it in silicon is from the
point of view of Coefficient of thermal expansion, or CTE.
So, silicon has a CTE of 2.5 parts per million.
What it means that for
every kelvin increase in your.
Temperature in your X direction the Silicon
chip will expand 2.5 parts per minute.
A PCB, the best of the
material that you can get has a
coefficient of thermal expansion which is at least.
At least five times greater than that of silicon.
So the minimum you can achieve in a PCB material is 15 parts per million.
So if you had a silicon chip placed on a PCB with very tight interconnections
and the silicon chip would be heating up your PCB, there would be large amounts of.
Stress built up into this PCB which is fine if these interconnections are far apart
but it can cause havoc if your these interconnects are very tightly spaced.
That's another reason why we use silicon as
the material of choice for making this interposer.