An Extreme Ultraviolet lithography machine costs $150 million.
That’s a lot of change. And it makes you wonder.
Is having EUV really that big of a deal?
You might have heard about this or that company managing to "achieve
7 nanometers" without the use of EUV. What should we make of that? Can we do 7nm chips without EUV?
The answer is yes, but you won't want to. And they probably won’t work as well. In this video,
we are going to look at why we so badly need EUV
to make the next generation of semiconductors. And what companies have to go through without it.
Prior to EUV, the leading edge lithography technology was DUV - deep ultraviolet lithography.
It uses an argon fluoride laser with its 193 nanometer wavelength to etch wafers.
I have been told that industry professionals say A R F
rather than "Arf". But I refuse to bend to their corrections.
ArF was first introduced with ASML's PAS5500 series at around the turn of the century.
This step and scan machine could etch for the 90 nanometer node generation. Improvements to this
technology helped take the industry from there to the 65 nanometer process node generation.
Over the past 30 years, the lithography industry went from using simple g-line
mercury lamps to i-line to powerful excimer lasers to etch on wafers.
More powerful light sources have improved resolutions and created more powerful chips.
Had things gone right, the industry would have smoothly moved from etching
with 193 nanometer light to 13.5 nanometer light when EUV came online.
But a funny thing happened. EUV started missing its delivery targets.
And it would do so for the next ten years.
Until the Dutch cavalry arrives, the industry found itself needing to squeeze more out of 193
over and over again. So the industry found renewed energy with the introduction of immersion
lithography, where you shoot that 193 nanometer light through water to improve the resolution.
ArFi, as I will continue to call it, first entered the industry in around 2007 with the introduction
of the ASML XT:1700i machine. This machine thus enabled the 45 nanometer process node.
But what will the industry do about the generation that comes next?
Let me pause here so that we can talk about what the nodes names are all about. For up until now,
the node processes had once corresponded to its smallest half pitch or gate length.
Moore's Law guides how the industry chooses its numbers. To meet Moore's density doubling targets,
each new node generation has to be 70% smaller than the next.
Thus, from 65 nanometers to 45 nanometers. The next scheduled node after 45 nanometers would be
the 32 nanometer node in 2009 - 70% of 45 - and the 28 nanometer node in 2010-2011.
But by this point, even with immersion techniques, ArF lasers cannot physically
achieve a half pitch smaller than 40-45 nanometers in a single exposure.
And the half pitch cannot actually get to be in the 7 nanometer range.
But such literal naming techniques wouldn’t be useful for marketing purposes.
So the industry decided to keep the shrinkage going. The headline number
would keep shrinking by 70% each generation, even though the half pitches no longer moved.
I have heard more than a few people cry out that this is dishonest marketing.
A few people want the government to get involved. Which I think is kinda amusing.
But I want to point out that simple half pitch lengths - like chip frequency numbers - no longer
meant what they used to long before 45. The goal is for the end user to know that this node
delivers better performing chips than the older generation. The smaller number still does this.
Anyway, now that the node names and the half pitch lengths are no longer the same,
I am going to refer to the nodes themselves from now on as N28, N10, N7, N5, and so on.
This is how TSMC does it in their corporate communications.
The actual, literal half pitches will continue to be delineated in nanometers.
I have digressed, so let's get back to business. So now that optical lithography
resolutions have bottomed out for now, does that mean semiconductor performance has plateaued? No,
the industry managed to produce better chips over the next few years. And that is for two reasons.
The first reason is that with the N22 process node in 2012, the semiconductor industry
transitioned to using a new type of transistor: the FinFET. FinFETs are a type of transistor that
is no longer planar. It is essentially 3-D, with multiple fins side by side and covered by a gate.
You do not need the intense engineering details - that’s
for a future video - but know that a 3-D gate FinFET can be
up to 2x as effective as an old school planar gate while using the same amount of space.
FinFETs are also the reason why Intel,
Samsung, and TSMC's node numbers are jumbled and not all that comparable.
Intel had been the first company to make the FinFET transition,
with the first N22 FinFET Ivy Bridge CPUs out in 2012. Samsung and TSMC
followed thereafter. When TSMC debuted their FinFET implementation a little later,
they decided to skip ahead from N22 to N16. Intel refused to do the same so there we go.
To keep things clean, I’m just going to use TSMC’s node terminologies. Gosh, this is confusing.
Part of the reason why FinFETs were so difficult to implement
is because their 3D structure interfered with the second big
reason behind improved semiconductor performance: Multiple patterning.
I have talked about multiple patterning before. At the risk of repeating myself,
this is where you use several mask layers in order to pattern a single design layer.
The industry started with what we call Double Patterning pitch split - sometimes referred
to as Litho-Etch-Litho-Etch or LELE - at about the N22 node process generation.
If you have a dense layout that cannot be handled with a single exposure,
LELE has you create two lower density layout masks. You then use two exposures
to superimpose the two masks and create a single finer image on the actual wafer.
The biggest and most fundamental problem is figuring out how to split a single design
into many. For double patterning, this hard work is performed in the background
by a specialized Multi-Patterning tool like Calibre Multi-Patterning.
So for human chip designers, it is like as if nothing ever changed. For now.
Double patterning by itself worked fine for the N20,
N16 and N14 nodes. But the node process generation after that required going an extra step.
With EUV still unavailable for the N10 node, the industry introduced
two new forms of Multi-Patterning: Triple Patterning and Self-Aligned Double Patterning.
Let's talk about the first one for now: Triple Patterning or LELELE pitch-splits.
This is conceptually similar to double patterning. You create three masks of
lower density layouts and superimpose them onto the wafer as one super-fine image.
Seems simple right? So why is Triple Patterning more troublesome than Double Patterning?
The problem is that a third layer introduces immense new complexities. EDA tools,
foundry design rules, and chip designs all need to be rejiggered.
The big problem is a computational one. Finding the optimal way to split the
final design into three masks is far more difficult than it is with just two masks.
Here is what I mean. Take a square.
A square has four nodes in it. With double patterning,
each of the two masks handle opposing sides of the square.
And with this four-node shape, there are 2 double patterning options available for coloring.
The EDA software thus has to check through them for design rule violations and what not.
With triple patterning, the number of variations
explodes exponentially. For that same square four node structure,
triple patterning has 18 variations rather than just two with double patterning.
A five node structure, 30. And so on. A semiconductor design can have
hundreds of different nodes and design variations.
The software needs to check through at least a good portion of these.
This problem is not solvable in polynomial time. In other words,
for you computer science nerds out there, it is an NP complete problem.
This is a massive slowdown, and in the end,
the chip designers themselves had to be retrained to change their design tendencies.
Triple Patterning also has an economic problem. Each mask is expensive and Triple Patterning
inherently needs 3 of them. Those costs add up. For instance, double patterning at the N20 node
increased the costs of the lithography module 50% from N28. Depending on whose cost model you
consult, N10's triple patterning makes its lithography module 3.85x higher than N28.
Triple patterning managed to get the industry to the N10 process generation.
However, I hope that I have made it clear that by now the industry is desperately
trying to keep its head above water until EUV arrives. So now we have come to N7.
N7 is another 70% node shrink on top of N10. EUV was close to being ready. But TSMC - by this
point the market leader, more on what happened to Intel later on - felt that it needed more time to
feel comfortable with this new tech before putting it to use for flagship customers.
However, N7 had to hit high volume manufacture in 2018 when the Apple A12 and Huawei Kirin 980 chips
ship. Thus at the start, TSMC had two versions of N7 - one with just multiple patterning and N7 plus
a little later using EUV. Afterwards, TSMC would transition into an N6 node.
So N7 is an interesting node - the final node conceivably achievable with 193i
technology. It is not cheaply achieved. The 193i version requires Triple Patterning as expected,
but also adds on something called self-aligned quadruple patterning.
Self Aligned Quadruple Patterning is a double dollop of the Self Aligned
Double Patterning or SADP - which I briefly mentioned earlier in this video but skipped over.
SADP uses chemical vapor deposition or CVD to apply chemical layers of
"spacers" to the sides of a template.
What does that mean? In plain vanilla lithography, you put a layer of resist onto a substrate.
You expose it to light and then etch the resist away. Nice, you got your lines.
With SADP, there's more work to be done. You add a "template layer" on top of the substrate, and you
do lithography on that first to create your lines. Apply resist, expose to light, etch, yada yada.
Then, the foundry uses CVD to add spacers to the sides of the original template
lines. Think of it like guard rails. Then you strip the inner template lines away,
leaving the deposited spacers behind. Etch accordingly.
The density is now doubled. Now you got something like a bunch of high density parallel lines.
Self-aligned Quadruple Patterning does all of this twice. Twice.
N7 is an unusual node too in that it breaks a number of prior design rules.
Thus, old chip designs have to be re-engineered to accommodate.
I wish I can explain this a little better. But trust me,
you don't want to know. I have read it ten times and I still don't get it either.
At this point, only a small percentage of the chip's total features are being actually produced
in one exposure. Self-aligned Quadruple Patterning imposes
additional constraints on the chip designer. As you might have guessed,
more parallel lines, with those lines' widths being fixed and not easily changeable.
Imagine trying to draw the rest of the effin' owl, but you can only use
fixed-width parallel lines. This is extremely restrictive and makes for less efficient designs.
Furthermore, error margins at this point are extremely tight.
Foundries have budgets for the amount of errors they can tolerate. But if you mess up the
relative placement of these critical edges, it is a failure mode and should be avoided.
Intel's N14 is roughly equivalent to TSMC's N10 in terms of transistor density. Intel's N14 would be
the node that broke its famed Tick-Tock strategy. It launched in 2014 and stayed as the flagship
node for years - until when it was finally succeeded by Intel's N10 ramped up in 2019.
Who really knows exactly why Intel's N10 ramp - which is
roughly equivalent to TSMC's N7 - took so long to come to market. But we can guess.
I reckon they tried to cross the N10 to N7 node gap without EUV, which means doing all the
multiple patterning techniques we just talked about in this video and more. Per Anandtech:
> Brian Krzanich has said that in certain cases the company needs to
use quad (4x), penta (5x), or hexa (6x) patterning for select features
as they need to expose the wafer up to six times to “draw” one feature.
I am not super surprised that it wouldn't yield. No wonder GlobalFoundries ditched their 7nm node.
EUV did not seem commercially viable until the 2014-16 time period, when ASML's insane
dual-shot laser pulse technique drastically improved EUV light source power output.
So I feel like Intel just got caught in a tough spot as first through the breach.
Now with EUV, N7 features can be produced with up to 30% better cost efficiencies right off
the bat - even taking into account the EUV machine's $150 million price tag.
In 2020, TSMC made a rare blog post to celebrate 1 billion N7 chips. They rarely do these posts,
so I think they must have thought it to be a really big deal. And I agree.
Something I learned while doing this video is just how fuzzy and vague
these node processes are between generations and foundries.
Not just their names, but also their physical dimensions and performance metrics too.
It is a reflection of the way leading edge chips are made now.
At this point, node manufacturing processes are worked alongside
the chip designs themselves - a methodology known as Design Technology Co-Optimization.
Everything is optimized and nuanced - the size of the fins and the pitches for instance.
Some are shrunk. Others are not. The design choices are as carefully
curated as your hipster's cafe - because everything has a trade off.
The magic of human abstraction is that they take all those nuances and sweep it under the rug
as a single number. Some website says that this country or that country has achieved "7
nanometers" or "7 nanometers equivalent". And we all start thinking certain things.
7 in one place isn’t the same as 7 in another.
We shouldn’t take headlines at face value. The devil is in the details.