Now let's start discussing shared memory and private caches.
And in order to simplify the discussion what I've
done is, I'm using the simplest form of the
shared memory machine that I told you about. That is
an SMP where there's a single system bus that
connects all these processes to talk to the main
memory. Now cache that is associated with the CPU
Serves exactly the same purpose in a multiprocessor like this,
as it does in a uniprocessor. And that is, the CPU,
when it wants to access some memor, memory location, of course, it
is going to go to the cache and see if it
is there. If it is there, life is good, it can get
it from the c, from the cache. If it is not
in the cache, then it has to go to the main memory.
And fetch it from main memory, and put it into the cache
so it can reuse it later, and that's the purpose that cache
performs in a uniprocessor. In a multiprocessor,
performs exactly the same function as in
a uniprocessor. By cacheing data that is
pulled in or instructions that are pulled
in from memory into the cache so that CPU can re-use it later. When
cache in a multiprocessor, associated with each
of these CPUs performs exactly the same role.
As it does in [UNKNOWN] process. And that is, if the CPU
goes to main memory, and pulls in some data, it's going to come
and sit in the cache. So obviously when the CPU is looking
for something, first it is going to come and look at the cache.
If it is not there, it's going to go to main memory. And
fetch the data and put it into the cache so that in
the future the CPU doesn't have to go to the main memory,
but get it from the cache itself. That's the purpose of the cache
in a uni-processor. Exactly the same purpose a
cache performs in a multiprocessor as well. However
there's a unique problem with a multiprocessor. The
fact that there are private caches associated with
each one of these CPUs, and the memory
itself is shared across all of these processors.
Let me explain that. Let's say that there's
a memory location y that is currently in the
private caches of all the processors. Well maybe y
is a hot memory location so all the processes
happen to fetch it and therefore it is sitting
in the private caches of all the processes. Let's say
that process P1 decides to write to this memory
location y now y is changed to y prime.
Now what should happen to the value of y
that is sitting in all the p caches. And clearly,
you know, in a multiprocessor, a multi-threaded program, there
could be a shared data structure that is being
shared with all the processors. And therefore if this
guy writes to a particular memory location it is possible
that that same memory location is in the private
caches of the peers. So this is referred to as
the cache coherence problem. Now someone has to ensure
that, if at a little point of time, if process
of p two or p three or any of these processes that happen to have this
memory location y, in the private caches decide
to access it. They should get y prime and
not y. Now who should ensure this consistency?
Here again there's a partnership between hardware and
software. In other words, the hardware and software
have to agree as to what is called the
memory consistency model. That is, this memory consistency
model, is a contract between hardware and software
as to what behavior a programmer can expect,
writing a multi threaded application running on this
multiprocessor. An analogy that you may be familiar
with is a contract between hardware and software.
If you just think about a uniprocessor, if
you think about a uniprocessor. There's a compiler
writer that knows about the instruction set provided by
the CPU. And the architect goes and builds a
CPU, and he has no idea how this instruction
set is going to be used, but there is an
expectation that the instruction set, the semantics of that
instruction set. Is going to be adhered to in the implementation
of the processor. So that, the compiler writer can
use that instruction set in order to compile high level
language programs. Similarly, when you're writing a multithreaded
application, you need a contract between the software
and the hardware, as to the behavior of
the hardware when. Processors are accessing the same
memory location. And that is what is called
the memory consistency model. And what we're going
to do now, is in order to get your creative juices flowing, I'm going to ask you
a question.