in this video we will focus on the steps
to deploy motor control algorithms to
fpga
we will show the workflow for the
generation of the hdl code
from the simulink model for the
field-oriented control of a permanent
magnet synchronous machine
in this simulink model the control of
the pmsm
is done by regulating the phase current
to control torque
the encoder is designed to capture the
dynamics at 25 kilohertz from the sensor
but in real world the encoder must
process the input in the megahertz
region
for incoming pulses this requires
achieving encoder sensor calibration
before the controller can achieve close
loop controls
to implement the encoder model on the
fpga fabric
make use of hdl coder's simulink library
which has
over 250 hdl optimized blocks and
additionally
hdl code generation is also supported
when your model designs are built
using simulinks library such as math
operations and other commonly used
blocks
such as logic discrete lookup tables etc
implementing the hdl model designs keep
the following in mind the hdl
implementation requires all block sample
times to be discrete
for generating hdl code create a design
under test
or dut subsystem which comprises of all
the model subsystems
which will be implemented on the
hardware logic
when implementing trigonometric
functions we recommend using lookup
tables
as they utilize a single cycle and it's
easier to define the symmetry range from
zero to half pi
once the simulink model is developed
partition the model
into hardware and software atomic
subsystems
or dots we have now introduced a very
fast dynamics into the original model
fpgas can run in the megahertz region
and balancing the latency is crucial
to propagate control signals through the
hardware logic
hdl coder inserts registers which ensure
the signals through the parallel parts
are coordinated and this process is
automated
to generate hardware efficient hdl code
from simulink
we require the data types to be fixed
point fixed point data types
is used in order to reduce power
consumption and hardware resource usage
for initial prototyping and validation
of control algorithm design
we can use floating point data type and
generate hdl code
hdl coder can generate hdl from native
floating point data type
this capability was awarded the embedded
award in 2017
for its ability to generate optimal code
without sacrificing numerical accuracy
when the project moves to production it
is recommended
that data type be converted to fixed
point
this data conversion is automated with
the fixed point designer tool
which will gather the range and coverage
of the design
and recommend fixed point data type
keeping the accuracy
and maximizing precision when high
dynamic range calculations are required
making it challenging to efficiently
convert it to fixed point
hdl code generation supports floating
point to generate vhdl
or verilog with our partition model
generate the c code for the processor
using the embedded coder
to generate the hdl code use the hdl
workflow advisor
we will complete series of steps to
ensure the hdl block contents are hdl
compatible
the advisor guides you through the
stages of generating hdl code
for the dut using a range of tasks when
the hdl advisor
completes its tasks you have
successfully generated hdl code
which is shareable and reusable
the hdl code generation report provides
details of resources hardware
optimizations
and provides traceability between the
generated code and the simulink source
model
prototyping is a natural next step to
build confidence on our simulation model
at this stage you've generated the hdl
code from the fpga fabric
and generated the c code for the arm
processor using the embedded coder
and would like to see it work on an
actual hardware
to prototype this implementation the hdl
code
needs to interact with the soc embedded
processor
via advanced extensible interface or
axibus
this axi target interface is auto
generated by the htl coder
which allows the embedded processor to
read and write
data from and to the fpga fabric
using the hdl workflow advisor set
target interface
port names and their respective hardware
interface
are populated and generated the axi
address mapping information
is also included in the c header file
which is generated by the embedded coder
additionally you can download hardware
support packages
for popular boards from xilinx and intel
which can fully automate the soc
programming
we have shown you how with no prior fpga
knowledge
you can take advantage of the advanced
tools from mathworks
and create the hdl implementations in
order to take the fast computational
requirements in your control algorithm
onto an soc device watch steven berowitz
from punch powertrain talk about how
they utilize hdl coder to implement the
complex controls for their switch
reluctance motor
to learn more about the hdl coder and
working examples of control applications
deployed on soc
visit the hdl coder product page on the
matworks website