A TAP controller is probably the most common block used in support of on-chip testing.
It is at the heart of a JTAG network. With the emergence of IJTAG, many SoC designs will
be using multiple TAP controllers for accessing internal logic during test.
Having a thorough understanding of the TAP controller is essential for most design-for-test
applications. In this instructional video, we will review the structure and operation
of the TAP controller. TAP is the abbreviation for a test access port.
It is part of the IEEE 1149.1 standard for JTAG.
The original motivation for JTAG was boundary scan testing. Boundary scan is a method for
gaining direct control of the I/O pins at the boundary of a chip during test. This enables
efficient testing of the interconnections between devices that are mounted on a circuit
board. Design-for-test engineers realized that JTAG
control need not be limited to just the boundary of the device; it can also be used to gain
access to internal structures during a test of the device itself.
JTAG offers two significant advantages. First, its serial interface requires only a minimum
set of test access pins. Second, because it's an IEEE standard, it facilitates design re-use
and standard protocols. A JTAG network typically has five I/O signals.
All data sent to the JTAG network goes through the test data input. All data read from the
JTAG network comes out the corresponding test data output. There is a single test clock
input. An optional input is the test reset signal. The remaining input signal is used
for determining the test mode state of the TAP controller.
The data shifted through the test data input can be directed to several different destinations.
One destination is the boundary scan register. Traditionally, these are the cells which encompass
the boundary I/O cells of the device. While a test vector is shifted into the boundary
scan register, data is also shifted out from the previous test vector so it can be compared
to the expected response. The data can also be directed to the bypass
register. This enables multiple JTAG networks to be daisy-chained, with the ability to pass
data through, unchanged. Besides the boundary scan register and bypass
register, there can be other registers available for loading and unloading, such as internal
registers for accessing built-in self-test blocks.
Before one of these registers can receive data, it must be selected. This is done with
the combination of the TAP controller and instruction register. Because it is central
to the operation of the JTAG network, let's look closer at the operation of the TAP controller.
The TAP controller is a state machine. The state machine can be divided into three sections.
One section consists of the reset state and the run test state. The two remaining sections
are essentially duplicates, except one pertains to the data register, and the other pertains
to the instruction register. Let's step through the state diagram to better
understand the interaction between the TAP controller and the rest of the JTAG network.
Let's assume a test reset has just occurred, putting us in the "test logic reset" state.
The value of the "test mode" input during a rising edge on the test clock will determine
the next state. While the test mode input equals one, we remain
in the reset state. Changing the test mode input to zero moves us in the "run-test-idle"
state. Changing the test mode input to one sends
us to the "select data register scan" state. As mentioned before, we need to first load
the instruction register so it selects the correct data register. We go through the "capture
instruction register state." We then perform one or more shifts, depending on how many
flops are in the register. The number of flops corresponds to the number of data registers.
After we are done shifting, we reach the "exit" state and then update the instruction register
with a parallel load. The values in the instruction register typically control multiplexers that
will channel upcoming data to the appropriate data register.
Next we follow the same seven possible states to load up the data register. Note that most
of the time will be spent in the "shift data register" state. For example, if your device
has 128 boundary pins, the TAP controller will remain in this state for 128 cycles.
After the data register is completely loaded, the TAP controller enters the "run test" state
and a test vector is executed. After the vector is executed, the data is captured during the
"capture data register" state before the next shift occurs.
One interesting aspect of the state machine is if the test mode input is held high, the
TAP controller is guaranteed to reach the "test logic reset" after five consecutive
clock cycles. This is an effective way to perform a soft reset of the TAP controller.
Now that you have a better understanding of the TAP controller, it should be easier for
you to comprehend the operation of a JTAG network. With this understanding you have
the essential knowledge that is needed to use other DFT methodologies such as BIST and
IJTAG.