Hello, and welcome to our video on Unit-Testing
an AUTOSAR Software Component.
Do you have an AUTOSAR Classic Component
which models calls to basic software services
and want to achieve coverage of the component?
Well, then this video is for you.
In this video, we will demonstrate
how you can use Simulink Design Verifier to analyze
your component at unit level.
My name is Alok, and I am a Developer
for the Simulink Design Verifier product at The MathWorks.
Here is a throttle position integration model
which integrates two throttle position sensor
components and a throttle position monitor component.
These components contain callers
to basic software services.
The sensor components take the raw throttle position
sensor value and convert it to a percent value,
whereas the monitor component takes
the values provided by the sensor components
and decides which signal to pass through.
Now, suppose you want to generate input test
vectors at unit-level for the Monitor component.
To do so, first we will open the Design Verifier
pane on the Simulink tool strip, select the component
under test, and then run Design Verifier Analysis.
As you might know, to simulate the AUTOSAR Component that
calls basic software services, we
need to insert reference implementations
of the corresponding services.
Simulink Design Verifier achieves this
by generating an analysis harness, which
contains Simulink functions that define these services.
A quick look at the harness indicates these functions
being defined such that they output any possible value
within the supported range of the output data type.
These values are controlled by the automatically inserted
root level inports, which are driven by the generated test
cases.
Another thing to note here is that multiple calls
to these functions within a single step
would return the same values.
Coming back to the analysis, you can
see that when the software completes
analyzing this harness, the Results Summary window
displays that the software identified 18 coverage
objectives for the component, and was
able to generate test cases that satisfy all these objectives.
These generated test cases get saved in a .MAT file by default.
But you can also choose to save the test vectors in a test
harness, by creating a harness model which
uses a Signal Editor block containing scenarios
that are comprised of the generated test cases.
Alternatively, if you have a Simulink Test license,
you can also choose to export the test vectors
to new test cases automatically created in the Simulink Test
Manager.
This way, you can build your test suite
comprising of test cases for different components
of your system model.
Do you know that generating input test vectors
is not the only supported analysis mode?
Design Verifier can also identify design errors
and prove requirements compliance of your component
model, depending on the analysis mode selected.
So in this video, you have seen how
to generate unit-tests using Design Verifier for a component
model, which implements calls to basic software service
interfaces using blocks from the AUTOSAR Blockset.
But you can also perform similar analysis when you have
a Simulink model created by importing an .ARXML file.
That's cool, isn't it?
Additionally, you can also use Design Verifier
to generate test input scenarios for back-to-back testing,
to ensure equivalence between models and their associated
code.
To learn more, you can visit our Simulink Design Verifier
product page on mathworks.com.
Hope you all enjoyed this video.
Thank you very much for your time.