The final topic I want to cover briefly is, is scaling of a NAND memory.
So this is eight gigabyte chip and you can hold it in your eight gigabyte chip.
I always keep confusing between bit and byte.
A gigabyte chip and you can hold it on
your finger and I want to cover three main challenges.
These are facing the scaling of NAND flash memory.
One is the scaling of your tunnel oxide thickness.
The other one is your parastics in your cell and finally the 3D
3D NAND architecture which is just around the horizon as.
So these are some of the scaling, challenges.
So, tunnel oxide thickness, it has been, it has become very
difficult to, scale it, especially scale it, below, eight nanometer.
These
because as I described earlier, if you have
[UNKNOWN]
dielectric, you get a lot of defects in it.
And you get stress-induced leakage, which tends to kill your retention of the cell.
If you if you try to scale your inter poly dielectric then
what happens is that Again you get a large injection of
carriers into it and also it degrades your coupling ratio.
So all of these dimensions in your gate start that are your tunnel dielectric.
Your inter poly dielectric, they become difficult to scale.
And because they become difficult the scale, it becomes different:
to scale the voltage you require to program a NSD cells.
So you still need a very high voltage and that's why you can't
even scale your STI, so you have to do that high aspect ratio, h,
The other thing which become even worse is your cell to cell capacitance.
And I'll, I'll describe that more in a few slides.
So this is showing the, the equivalent oxide
thickness as different here than we talked about making these
logic transistors and The green line is for is for
you can see that you know to scale from 10
nanometer to 95 to less that a nanometer in 2010.
Because we wanted to shrink our gate
length, we wanted to keep the same electrostatic.
So we kept on shrinking this this oxide thicknesses for CMOS.
But look at what's happened in that NAND you know.
So these nine transistors they, their tunnel
oxide thickness essentially was ten nanometer in 1990.
It was eight nanometer in 2011, and it is still eight nanometer in 2010.
So think about the electrostatics of these transistors right.
Their gate length is 19 nanometers and they have 10 nanometers of gate dialectic.
So they have
really poor electrostatics but since it's not a logic device you really don't care
about electrostatics. But this has, this has become one of the.
One of the you know, sticking block of scaling.
And that is off research which is going on, so people are trying, instead of using
just oxide, why can't I use oxide nitrite? And maybe I can even
lower, I can have a slightly higher physical thickness but a lower EOT.
So I can maintain the same same retention but I
can program it much faster because then I'll be programming it.
I'll be just seeing the barrier through my outside.
So this is all of research which is going on in
the area of band engineering of tunnel oxide.
But nothing has, you know, nothing has been which
has gone into production yet. Because essentially this, this oxide is
Very key the high quality in this oxide is key because this is the oxide through
which your electron will tunnel in and out more than 100 k times.
And if, if you develop traps over here, you'll essentially degrade your retention.
You'll be also closing your program in this window so.
That's why people have tried to ki, they have changed
everything about the server, they haven't changed the tunnel, tunnel dialectric.
Because anything you replace, you replace, your silicon oxide with anything
else just your retention, you're not able to meet your retention requirement.
[COUGH]
The other thing which has become worse is
your floating coupling between these two adjacent floating gates.
So the other big problem in scaling is the parasitics.
So shown here is this nine area and you have the multiple of the transistors.
things were fine when these these, these transistors will fall apart.
But as you bring them
closer, the capacity coupling between them starts to become a problem.
So, if you are programming one of these cells it drives
up the voltage in the other cell and it tries to
program as well, so That's, that's, you know, there's a big
problem which occurs because of this
coupling between these two adjacent, gates.
And, we have been avoid, as I show you one way to avoided was, we are wrapping this
wordline around our cells.
So, if you look around the volt line direction it, it drops around the cell.
So one thing it does, it reduces your,
it increases your gate coupling ratio but the.
Another good thing it does it decreases
the coupling between your two adjacent float.
So if you look over
[INAUDIBLE]
that line is wrapping around you don't get as much coupling.
As compared to the other direction where that line is not wrapping
around That is along your, your world line is going this way.
So you, and you have a tall floating gate, so
you get a lot of coupling between these two adjacent cells.
And that is becoming a problem.
Another thing which is becoming a problem is that Since
you wrapped that line around to increase your gate coupling
ratio, you need a certain thickness to wrap it around, right?
So you have at least this inter-poly dielectric is let's
say 78 nanometers thick, and you have two of these.
So you need at least, you know, 50 nanometer of
spacing between these two lines just to achieve that wrap around.
And if you want to scale your cell below that, then again that becomes a problem.
So these are all, all open challenges right now.
And the parasitics as I showed you
it's becoming even bigger bigger and bigger problem.
[COUGH]
So.
One way to get around is, your parasitic, is to insert, airgaps.
So if you have a airgap, that's a material that has the
lowest, dielectric constant, and, again, people have been doing that as well.
So between these two floating gates, you essentially instead of
filling it up with dielectric You intentionally introduce this airgap.
And there's quite a bit of technology that goes
into, achieving that airgap so uniformly between these two cells.
And we'll talk about that next week.
But airgaps are routinely used in
your flash memory to reduce these uh,parasitics.
And the last thing which I just want to mention, and then, I'll
post a couple videos about, is that if you can't scale them, laterally.
Then the other way to scale is simply go verticle, right.
So, all of these vertical architecture, the, one of
the main selling point is that you can have larger lithography features.
So you can these features on this could be hundreds of nanometers.
But you could increase your number of bits just by increasing the number of layers.
So you can have a vertical pillar, and you can have, you can have 32 or 64
cells, just by having multiples of these layer's which are forming your cell.
So this is one of the main selling point of of going 3D.
That you can control your cost, not by the
target fee, but by controlling the number of layers.
And so that, it's a different
patterning shift when you go to these 3D devices.
That the main selling point is you want to get rid of lithography.
But at the same time you want a lot of these layers, right?
So, that's yeah the current number is somewhere around 64.
I'll tell you two layers of this, of this transistor that's stack vertically.
And this is the active video of research and I post different
videos about it.
But each of these companies which has in the flash business
how the different architecture, or other different methodologies for doing it.
So, I want to end it with this okay, so let's end with this small
you know, what I call, like to call is a crystal ball of any memory device.
Whenever you have a memory device, you
want to look at all these different parameters.
You want to look at how.
How is it, is it non-volatile if I switch off the power?
does it say there, how fast I can be ride into it.
What is the maximum bandwidth I can read and write to it?
What is the endurance, right?
What is the retention time?
What's the maximum temperature I can operate at?.
What are the cell size right?
So these are all, it seems most compatible especially if it's an embedded memory.
So let's start at how does NARA compare. Is that non-Volatile?
Yes, right. Is it fast enough?
What is the What is, cycling does, what is the endurance right?
So can anyone recall how many times I can read and write it?
Yeah. So let's look at some of these numbers.
You can read and write it 100,000 times, or ten to power five.
It's non-volatile,
that's the read and write time.
For, so you can read it at 25 milliseconds.
You can write it at much smaller speed.
So if you do that exercise and try to transfer that
file and read it back you'll see that you have those times.
The bandwidth again your, if you transfer your file into your
USB it will see it somewhere around, 25 megabits per second.
Let's look at our attention right?
So why is the, look at these numbers, so it's, it's not exactly 10 years
uh,especially for an MSC cell it's not 10 years, it's actually around eight year.
The energy we really didn't talk about it but its 10 to power
4 pico joules for, for each of these right and it is operational.
And you can calculate we'll have a, a homework problem
[INAUDIBLE]
calculated and you've calculated for a hard desk drive.
So hard desk drive is.
It's typically in order. It's much higher as compared to this.
So, it's a energy efficient device to read and write.
How about the maximum die size
available.What is the maximum die size available?
Yeah, 16 gigabyte or 128 gigabit.
Cell size minimum. 4F
square? 4F square, right so.
So 64 it's actually the cells here old chart so it's now 128
gigabit or 16 gigabyte per diode, features sized 4F square.
Yeah and you know,
flash is around a dollar per gigabyte. So essentially flash
it runs on all these metrics and there, there are a lot of competitors
to flash memory. So there's full alphabet,
[UNKNOWN]
there's facechain, there's RAM, there's. there's conductive bridge RAM,
there's you know any alphabet you can name I can name a memory which is computing.
[LAUGH]
Please
do attend on Wednesday, it should be
another exciting guest talk Soprano Galaxy talk.
I'll, I'll either choose from a person who has worked
on it from a long time, so it should be fine.
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