Hello, folks.
So what I want to do in this video is
to talk to you a little bit about, Self Aligned Contact.
Why do I need them?
How do I make them and what are the implications on my device?
So Self Aligned Contact, and we can also
call them, SAC, because who doesn't like three-letter acronyms?
So, what it means is it means
that my contact to my source and drain is now self-aligned to my gate.
So, traditionally in semiconductor technology, if you have a transistor, you
used to have this contact, and it connects your source and drain.
And it needs to be, you know, far away
from your gate, at least seperated by a respectable
distance, so it does not short with it. What the self aligned contact scheme
means is that my contant is essentially self aligned to my gate electrode.
And it could very well land somewhere like this, where it
touches my gate electrode, and it does not call the shot
and this transistor should still function. So it means this contact has to be now
self-aligned with respect to this gate. So, why do we need this here ?
So why, why do I need to bother about this?
So there are two reasons I want to point out that one thing which is driving the
need for these self aligned contacts is is our you know the task
master called Moore's Law. So if you look at Moore's Law it
essentially requires me that, you know, I, I'll reduce keep
on reducing my gate pitch by this very aggressive
amount and I reduce it by half in every technological generation.
On the other hand when we talked about scaling, we saw that
the gate length isn't really friendly to Mr. Moore and the physical Gate length for
our transistor rate has really been scaling
only as 0.9x with a real technological node.
So, a 30 nanometer tecnhology node has a gate length of you
know, around 30 and even at 21 has somewhere in that same range.
So, what has been happening is these
contacts have been coming much closer to the gate.
So, over here is a, I supplied these gate length plus
the distance for a two spacer, for this is you know, you gate length per two spacer
and the, this is plotted over is the pit, so if you subtract the gate
length plus two spacer, that is the amount of space left for your contacts.
If if you look at 90 nanometer technology it had you know 120 nanometer of space for
my gate and spacer and I had 200 nanometer space to land these contacts.
If I had a transistor I had you
know 200 nanometer space to land these two contacts.
And so this was quite okay, but what has been happening is
that this pitch has been scaling very aggressively, so
the space I have for landing this contact has been
decreasing by a very aggressive pace, and you can see
that in a 30 nano meter, 32 nano meter technology.
I only have, 30 nanometer left to line these, contact.
And if you continue this, same path, which doesn't look very sustainable.
What it says is that,
in 20 nanometer technology
, you certainly have no space to land these contacts.
And these land, these contacts have to now land on top of, your, gate.
And this is one of the reason that, you know, there's no space,
left for these, contacts to, you know, land, freely when this, leaving this.
Space between my contact my gate, so I need to go to this self-aligned scheme.
Another, another big
thing, you know, which is very important, and
you can only understand if you understand lithography is
that one of the reasons which is again
driving this self-aligned contact scheme is these overlay issues.
Let's say you have, you know, this your gate lines and these these
other ones are, you know, your contact lines, or could be, you know,
very much the other way around. So this you know,this set of grating which
you could be defining by pitch-doubling, say self-aligned double patterning.
But then you have these contacts, and these contacts are essentially they are
too close to each other so they have to be placed on separate masks.
And you will have some misalignment between each of these masks,
and this your bottom of, get electrodes.
And that was fine if you had, you know, one
mask, but if you have these you know, if you have
four different masks for patterning these contacts, you have to
align manage each of them to, you know, line up correctly.
So these overlay shoes are becoming again very, you know.
They require you to build these self
aligned schemes, so even though if you have
a large amount of misalignment and you align somewhere
else, you still make sure that you lined up
and that make contact to your source and drain.
So these two reasons you know if you look at just these two charts it became very
clear that at 22 nano-meter technology there was need to move
to a self-aligned scheme.
And in fact that is what happened, and if you
look at this announcement from Intel on their 22 nanometer
technology, that, you know, one of the titles of the
paper said that self-aligned scheme was used for this technology.
And this is one implementation showing how, this could be done.
So in their technology they use a high metal gate, so your gate is in fact metal.
So if your contact comes and lands over here,
your contact comes and lands on top of your gate.
It will essentially alert and shock between your gate and your sol-jay.
So, definitely, we don't, want to do that.
So what they do is they add three extra processor steps to
make it, self aligned scheme.
So, what they do is, they have this, they,
make this, gate, gate electrode and they recess it back.
And they fill it up with nitrites.
So this is filled up with nitrite and you nicely polish it.
And now, you know, your your contact to your gate is made somewhere far away.
It made,
you know, not in this plane but somewhere behind this plane.
And now in your contact, I come and land on top of your gate, so they
have this nitrite which safely prevents it from
shorting to this gate electrode or this gate metal.
So it's shown over, and by using this nitrite they
are able to achieve this SAC or this self aligned screen.
But it comes at the cost that you add these Three extra process
steps. And shown here is you know, the, the main
you know the main advantages is that you get with this self-align scheme.
And shown here is an actual TEM picture which shows that, you know,
It's not the best day for the contacts, they aren't having their best day.
So they're you know, quite a bit misaligned.
They were supposed to land somewhere here, but this
contact misaligned and it pushed out in this direction.
But since we are using this self
aligned scheme, part of it could still line on the source.
And then.
And over here, and you essentially still are able
to maintain maintain contact with this transistor over here.
So, you, it shows that, us if you didn't have a SAC, and you,
you're you're essentially, if you had some misalignment, your percentage of your dies
in your wafer Would just fall off along this cliff.
But if you have this SAC scheme then you essentially, even though you have this 15
or 20 nanometer misalignment, 100% of your transistor are still connected.
And your dies are, you know passing qualification.
So this is, one of the, you know, this is
one of the main advantages of going to a SAC scheme.
So what's the catch of, with the SAC scheme?
So one of the things which become worse if you
go to a self-aligned contact scheme is essentially you're parasitic.
So you're coupling between, this is your
gate and this is my source in-drain contact.
So I get a lot of coupling between
my gate and this this this consortium drain contact
because this is the all that is separating this contact from
my gate is is just the spacer material over ahead.
So that increases a substantial increase in this capacitor
coupling between my gate and my drain. And shown here is this
simulation with our from synapses and as expected, it shows
that, you know, this gate to contact coupling.
Could be in fact even bigger than my gate to my channel or gate to my fin coupling.
And that's of course not good.
It's not good for the little circuits especially not good for analog circuits.
you get some relief to this by by when you etch
your metals so we remember we did a metal etch pack to
form our Of our sack, so this reduced the height of
this gate metal from tall to at least made it slightly less tall.
So that helps to an extent in reducing
this fin capacitance, but still that's a lot of
fin capacitance that you add, not fin capacitance,
but the capacitance between your gate and your contact.
You increase that substantially,
but none the less there's no other option left
so you know we go off the options we have and people
have implemented this in technology.
So, when this announcement, came out later last year, you know
Intel made a lot of brouhaha about, implementing this SAC scheme, and
so then you know the nan guys, the flash guys, and the DRAM guys,
they came from the wood works and they say hey, hey, hey, you know, we.
Whats the big deal?
You know we have been doing this since a long time and in fact that is
the case whats shown here is the NOR flash technology from 45 nanometer.
And again, you know for a NOR flash you need this
red line contact to line between every two adjacent cells to connect to that cell.
And they did in fact have been using this self-aligned scheme.
So that's shown in this tungsten contact and it aligns in this self-aligned way
between these two these two two flash cells.
So they have been using it for 45 nanometer.
And then you know suddenly the DRAM guys came and
say you know hey, hey you know what's the big deal?
You know we have been using it even longer and in fact shown here this scheme from
65 nanometer DRAM technology and it uses this one transistor one capacitor.
The capacitor in the scale, trench capacitor,
it's, digged into a trench inside your, silicon
and surely enough, you can, so this is
your capacitor, this is your, transistor and you
can see the bit line contact which is
connecting to your transistor, it's itself aligned and it,
It lines up on top of your gate, when it, in this case it's a bunny gate and you can
see that you know, it clearly is self aligned with respect to this transistor.
So clearly you can
see, you know, some, another point I want to drive home is that, you know,
once we have learned enough to see some common grounds and some common scheme.
And this SAC scheme is suddenly you see a sprinkling over from DRAM to,
to your NOR FLASH to your 22 nano-meter Intel logic technology.
And you see that, you know, this Moore's
law and this alignment requirements are driving this to
become more and more pervasive across a variety of technologies.