Often, you need to verify your RTL design
against a specification or a golden reference.
With a MATLAB or Simulink reference model,
your goal is to verify that the behavior of the RTL
matches the model.
HDL cosimulation is a feature that
enables you to bring your RTL within MATLAB or Simulink,
and co-simulate using HDL simulators.
With automated workflows, save time building test benches,
confirm your RTL for bit and cycle accuracy,
and discover bugs earlier in the design process.
We have previously supported Siemens, EDA Questa,
and Cadence Xcelium simulators.
Now we have added support for AMD Xilinx Vivado simulator.
Hi.
I'm Marc Erickson.
In this video, I will show you the automated workflows
for HDL cosimulation using Vivado simulator.
You can bring in an existing HDL implementation
into MATLAB and Simulink using our Cosimulation Wizard.
When using HDL Coder you can generate an HDL implementation
and a verification test bench directly
from the graphical workflow advisors.
Use the Cosimulation wizard to guide you
to the creation of a Simulink block or MATLAB system object
for your existing HDL design.
We select Vivado simulator and add the HDL files.
Here, we create a Simulink block for a raised cosine filter
design.
The wizard creates a Vivado project
for compiling and elaborating the design,
automatically determining the top level and its interface.
We select the debug option for Vivado waveform capture,
and then elaborate a shared library
for integration into Simulink.
We define a clock and reset internal to the block
so that we do not need to do so in Simulink.
We specify the output data type information.
We specify the timings of our internally-generated clock
and reset waveforms.
The Wizard gives us a visual of the relationship
of inputs, clocks, resets, and the cosimulation start time.
Lastly, we equate the Simulink sample time of one
second to the 20 picosecond clock we defined previously.
We finish and integrate the HDL design
into our Simulink test bench.
The cyan block can be used to recompile the HDL design.
We simulate and check the behavior is as we expect.
Open the generated waveform database in Vivado
to debug internal design behavior.
The same workflow can be executed for a MATLAB system
object.
After using the graphical wizard workflow,
it is easy to reuse your settings
to regenerate a block or system object using the command line
interface.
The same steps are run as in the GUI and output to the MATLAB
console.
HDL designs with the same HDL file set
and HDL port interface simply need
to use the cyan block to recompile.
When other HDL design changes occur,
make incremental adjustments to the configuration object
and rerun the generation workflow.
It is also possible to use the command line interface
to automate the creation of a library of IP blocks
to avoid the tedious process of clicking
through the graphical environment for each design.
Use MATLAB testing frameworks to create
complete MATLAB-based test environments that automatically
handle HDL design updates in a continuous integration
workflow.
When creating designs in Simulink
and generating the HDL using HDL Coder,
creating a co-simulation test bench model is automatic.
Load the HDL Coder tool strip, select the Vivado simulator,
and generate the test bench model.
The various Wizard parameters are
generally unnecessary since the full design context is already
known.
Just run the model.
Scopes and Assertions will alert you to any miscompares.
Similarly, the MATLAB HDL Workflow Advisor
can guide you through the entire generation and verification
process.
Select to log signals and run the cosimulation.
Figures and assertions will alert you to any miscompares.
Vivado simulator support is just the latest simulator
in our suite of code simulation links.
We have a whole portfolio of examples developed
over many years that can show you how to best use our tools
to verify your HDL.
We also have many other tools to help you
with connecting MATLAB, Simulink,
and your HDL workflows, export behaviors
to SystemVerilog or SystemC.
Export a Simulink test bench to a complete SystemVerilog UVM
test bench.
Prototype and debug your designs on FPGA development boards.