So guys in the previous lectures, we have talked about the NAND cell.
And it's operation.
And advances in the field of planar NAND technology.
In this video I want to motivate why do we need to go from a planar NAND
technology to a 3D NAND technology. So shown here is a few.
Open up any of your,
NAND, flash memory chips that's in your iPhone or your iPod.
And you drill down and take a TM of an array of NAND array.
This is how it looks like for you.
This is the TM along the word-line, so you're along the word-line.
It essentially looks like the skyline of Manhattan.
It has a lot of these skyscraper cells, and
they are becoming taller and taller and thinner.
So each of these, each of these is.
Is a one cell, one NAND memory cell.
And I, I'm plotting this in more detail over here.
So this is, you know,
expanded view of this, of a few NAND cells.
And And this is showing the different
parts as we discussed in our previous lecture.
So this is, this is the, this is the silicon.
And it, the two adjacent cells are
separate by this, shallow trench isolation or STI etch.
And then you see this floating gate which is floating
and not connected to any of the terminal so which
is used for storing the charge over here between the
floating gate and the silicon you have your tunnel oxide.
which is used to tunnel the electrons from your
silicon into your floating gate as we discussed previously.
And then over here, you have this blocking oxide,
which prevents these electrons from getting outside.
And you have this control gate which
is, you know, wrapping around your floating gate.
So this is as we discussed previously.
the traditional way people have been shrinking NAND flash memory,
decreasing the cost per bit, as I said, scaling, scaling this individual cells.
So they have been scaling the size, the
feature size, of this individual NAND memory cell.
But increasingly we see that, you know, this approach is running out of steam.
So why? So I'm showing here a schematic
of this one single NAND cell that we just described.
It has the, it has the silicon then it has analog side, which which controls
the tunneling of electrons and into the
floating gate and out of the floating gate.
And then you have this blocking oxide and then you have this control gate.
So if,
if I plot the, if I plot you
know, the band diagram along this particular direction.
This is how it would look like.
So you have you know, you have the silicon.
Here and then you have your tunnel oxide then you have your floating
gate then you have your blocking oxide and then you have your control gate.
So with the scaling of this NAND flash memory cell, I would like to scale
it both horizontally.
And also, I would like to scale it vertically, right?
That's the way I would like to scale any device, I would like scale it vertically
reduce it's height, and I would like to
scale it horizontally and reduce it's feature size.
So you know, that, that's the way, you would imagine, you would
scale any, any device, you would, you would scale both its dimensions
but looking past looking, you know, looking for
the past few
generations of NAND flash memory cell. It has mostly scaled horizontally while
it has been of very difficult to scale it very difficult to scale it vertically.
So, why, why this is the case. The primary driver for that is, it's not
possible to scale this tunnel oxide any further without compromising, you know,
the performance of the cell. So, why this is the case?
Here, this tunnel oxide, as we
discussed previously, this regulates how the electrons.
Come in to your floating gate and how it regulates how these electrons.
go out and you erase your cell.
So the problem has been, it's not possible to
scale this without compromising the retention of the cell.
So you know there'll be homework problem discussing this further where you
would you know calculate your retention time based on your tunnel oxide thickness.
But as you can you know intuitively expect you know if you scale this
tunnel oxide it becomes very easy to, for your stored carriers to leak out.
And flow back to your silicon, and it would
not be possible for you to meet the retention
requirement of whatever the retention requirement is.
if you meet the retention requirement of, you know, a few
years
for each cell. So this, this has, you know, the, tunnel
oxide scaling has, I'm not, you are not being able to scale the tunnel oxide
This has limited the overall scaling of your cell.
So if you can't scale the tunnel oxide
you can't scale the cell, vertically you probably can't scale
the, the voltage applied on your control gate to program and
erase your cell.
If you can't scale that, then you can't also scale the STI height.
Because if you have the same voltage you need this STI to be to be a certain height
to provide isolation between two adjacent scale, between two adjacent cells.
So it has not been, you know, able, it has not been possible to scale
this cell vertically. But we can still keep we can
continue scaling by just horizontally scaling the cells here.
All we care to know how many, how many cells you can fit in the.
In a given area that, that determines the cost here.
As long as you can keep it
scaling horizontally, you can still keep reducing your
cost per bit.
What's, what's the problem with this approach?
What's the problem with just keeping on scaling it horizontally?
So one of the problems, you know, with just scaling your horizontal dimensions.
Is now your, floating gate volume, or you know, the area of your floating gate,
it decreases with each technology node. So for current technology of 20 nanometer
flash technology, your floating gate would be
approximately 20 nanometer by 20 nanometer in horizontal
dimension.
And these dimension, at these dimension, your floating gate is only sufficient
has sufficient capacity to only store maybe you know, 15 to 20 electrons.
And even this keeps on decreasing as
you keep on decreasing your horizontal dimension.
So one of the main problem is now you have a lot of cell to cell variations.
You, so we talked about multilevel cell before so you
know, imagine you had, four bits stored in this one cell.
So, you know, each of this bits would be, you know, now
determined by this 20 by four or, you know, five electrons.
So, you know, it's, you know, it's, it's, you can imagine, you know,
between two cells or, you know, between two states it becomes much more this,
much more difficult, you know?
if your charge state is just being stored by five electrons.
Another problem is, now your cell to cell capacitance.
So you know you parasitics increase. So you know, traditionally.
the way they have been controlling parasitics is by wrapping this
control gate around your floating, and that's one way to, you know,
decrease your cell-to-cell parasitic.
So, you know, one way to decrease this cell-to-cell capacitance.
So, you know, cell-to-cell parasitics, is to, you
know, wrap this control gate around your floating gate.
But as you can imagine, you know, if
you keep on scaling in your horizontal dimension there
is not enough, there's not enough space left
for you know, this control gate to wrap around.
And your, you know, your cell to cell,
your parasitic capacitance between two alternate cells will increase.
So you know that's another.
Thing which limits this horizontal scaling.
So another factor which has been necessitating the need for, for 3D NADN is
actually you know the cost of lithography. So, shown here is essentially,
you know, the cost per bit of a NAND cell.
And you know I'm taking this courtesy of this paper, from Toshiba Which
shows, you know, that the cost per bit of your NAND flash cell has
been going down very consistently at the rate of 40% per year.
So, for a gigabyte of memory, for NAND flash memory,
which costs, you know, a dollar in 2012
would, it's only expected to cost $0.60 in 2013.
And that's why you know, your in all of your mobile
phone and your iPad and your tablet devices you know, they keep
on increasing the capacity every year without any increasing the price
because you know the cost per cell, it just keeps falling at
this 40% per year. But, you know if we keep on scaling our
horizotal cell dimension, we require. More and more complex lithography steps.
So you know, already the NAND flash memory, it
has, you know, already become the driver of lithography.
So it was the first to use double-patterning and you know.
It's it's
also you know the fourth to use quadruple patterning, and
so it's, you know, the, it has been, become, the NAND
flash has become the prime driver for lithography going forward,
because it has the smallest feature sizes among all semiconductor devices.
And as we are going to, as we discussed in one of our previous lectures.
You know, that going to all these
advanced lithography, double patterning and quadruple patterning,
it requires a lot of process depth.
So you know your cost just keeps on increasing.
And you know also there is lithography tools are expected
to you know cost more and more so you know again.
You require, to pay, you are required to
pay more for these lithography tools, so, you know,
these, because of these lithography tools, and, you know, the cost of doing
all these, complex lithography steps, you know?
This paper predicts, you know, that very soon, it might
not be able to keep on this 40% decrease per year.
And your cost per bit if you keep on doing just planar
NAND might actually start going up.
So this, you know, necessitates the need for, 3D
NAND, or, you know, going to an alternative to NAND, which,which
which provides this cost decrease which keeps on providing this cost decrease.
So I'm, I'm showing here, you know, one of the implementations of this 3D NAND cell.
This one is from
Toshiba, and it's, you know, it's called a Bit Cost Scalable Cell.
So you know the, the prime one thing to point is you know, in, in your, in your
2D or your planar NAND you know, your cell is determined by lithography, right.
The size of your cell is determined by lithography.
And at 3D cell, you know,
as seen here, what happens is, you know,
you are cell are, you know, your dimensions
of your cell are determined by these layers which,
you know, you deposit on top of each other.
And then, you know, you pattern them together in one step.
So, you know.
in your 3D nand technology, the cell is
not defined by these deposition of these layers.
So you know, as, as you know as, as you you know, you can predict your deposition
steps are much cheaper than lithography step, and so now your cell is now being
determined by deposition so it again, you know, brings down your cost.
And, you know, this is shown over here, so you
know what, you can control, you know, have this additional
level
you have this leverage where you know, you can control the
cost of the sale by, just by increasing the number of layers.
So you use the same lithography but now
you have multiple number of these layers which determines
you know how many cells you get and you can just keep on decreasing this bit cost.
That's why the Toshiba, you know,
very cleverly named their technology bit cost scalable technology.
So shown here is, you know, one of these arrays showing, 3D
NAND flash array and you know these these control
gates which are now determined by again, you know, these
deposition steps.
And you know the spacing between these
two alternating cells is also, you know, determined
by, you know, the thickness of this
layer which you deposit between these gate layers.
And you know the next couple of lectures we'll be talking in more detail.
The next couple of videos I'll be talking in more detail about you know
how these , what these different, what the function of these different layers are.
And you know how to manufacture
this 3D lens.