Liedtke, the author of the L3 microkernal, suggests tricks for exploiting the
hardware and avoiding TLB flushes, even if the TLB is not address space tagged.
And in particular, Liedtke's suggestion is
that take advantage of whatever the architecture
offers you. For example, the architecture may
offer segment registers in x86 and PowerPC,
both of them offer segment registers. What the segment registers do is give
an opportunity for the operating system to
specify the range of virtual addresses that
can be legally accessed by the currently
running process. What that means is, even
though you have a linear address space, that is, a linear virtual address space.
You can carve out that linear virtual
address space among several different protection domains by
using segment registers. So, here is the
linear address space provided by the hardware, starts
from zero to a max and that max is, of course, decided by the number
of bits you have for addressing in the hardware architecture. If it's a 32 bit
architecture, you have 2 to the 32 as the maximum addressing capability of
that particular processor. If you have 64 bits, you have 2 to the 64 as a
maximum address space that's available in that
particular architecture. So that's the linear address space
that is provided by the hardware. If
the architecture, such as the PowerPC, offers segment
registers to bound the range of virtual
addresses that can be legally generated by
a running process. Then use segment registers
to define a protection domain. So here is
one protection domain, S1, and it uses
segment registers to say that this particular
protection domain can generate virtual addresses starting
from here to here. Any other virtual address
generated by this guy is illegal, and the hardware will check that, because the
segment registers are hardware-provided facility for bonding
the range of legal virtual addresses that
can be generated by this protection domain.
Similarly, another protection domain, S2, can use
the segment registers to carve out a
different portion of the linear hardware address space.
So, for S2, the bounds for legal, virtual addresses that can be generated by, a
thread that is running, in this protect domain, starts from here. Ends here. And
so on. So, in other words, we can take the hardware address space that's
available. And using segment registers, provided by
the hardware, you can carve out the hardware
address space into these regions. And once we
do that, there is no need for flushing the
TLB on a context switch. Because, even before
we consult the TLB to see if there is
a match for a particular virtual address in
the TLB, segment register will act as a first
line of defense. And say that, oh, this address
is kosher. This address is not kosher because it
is not within the bounds of legal addresses that can be generated by this
protection domain. In other words, the segment
bounds that we're talking about are hardware
enforced, so this works really well. If
these protection domains are fairly small, meaning
that the amount of space, memory space,
that is needed by any given protection domain,
is not the entire hardware address space. But it is a
portion of the hardware address space. So we're able to carve
out the available hardware address
space among multiple co-resident, protection domains,
in the hardware address space, using these concept of segment registers.