The next paradigm shift which is happening in the field of packaging of
chips is going to this thing called 3D or 2.5D packaging of chips.
So what is driving this next paradigm shift?
So, as we discussed previously, most of the
previous changes, most of the thing in the
past, which have changes in which have occurred
in the field of packaging have been driven
by this IO. Or the number of input output connections
required to your chip. So we saw traditionally that you used to
use this quadruple flat packages. And since the number of I/Os needed could
not be meant met by this QFP package we move
to this Ball Grid Array packages. Which could enable a higher number of I/O.
And then but going forward, that changed, the next
evolution was the Flip Chip Ball Grid Array packages.
So this flip chip ball grid array
package can support up to 1,000 input-output connections.
roughly in the range of you know 1,000 to 1,500 I/O connections per chip.
But increasingly, as we are adding more and more
functionality into one single chip. It requires going to you know,
more than the number of I/O's which can be supported by this flip chip packaging.
So that requires going to this next evolution in terms
of chip packaging. the second thing which is driving this
change is now improvement in the system performance
which is, which is enabled by going to this 2.5D or 3D packages.
So there's this term which is frequently used called the Memory Wall.
So the overall system performance is limited by the bandwidth at
which, which, at which your CPU can communicate with your memory.
So you know, a CPU traditionally works you know, it has been working
at it can process the instructions very fast. But the overall system performance
is limited by, limited by the bandwidth it has in communicating with the memory.
So this bandwidth, this number of bits that you can transfer
between your memory and your CPU. So that depends upon,
that depends upon this interconnect of, of interconnect between the memory and the,
the CPU by this simple formula. So this bitrate it's very simple formula.
It's proportional to the area of your interconnect, and
it's inversely proportional to the square length of your interconnect.
The way things have been evolving in the interconnect space,
is the area of this interconnect is actually becoming smaller.
So the interconnect is becoming skinnier.
And at the same time, the interconnects are becoming longer.
So they are becoming longer, so this length has been increasing.
So both of these limit the bit rate that
you can achieve between your memory and your CPU.
And using
packages which uses wire bond.
So these wire bond, they can be the, the
lengths of these tend to be in the millimeter scale.
And they again tend to limit the overall bit rate that
can be achieved. So, going to, going to 2.5D or
3D, it, it, it enables significant reduction in the lens
of these interconnects.
And that's another driver to improve the overall system performance.
Another thing, another factor which is driving this
2.5D or 3D trend is the heterogeneous integration.
So if you open up your smart phone you
have different chips, you have a micro processor, you have
different kinds of memory you have a DRAM, you have a NAND flash..
Then you have different chips for doing wireless, and so,
basically, you have these different
chips, which are achieving different functionalities.
And there, there can be only two ways you can enable you can enable
heterogeneous integration. So, one of them is essentially going
moving more and more of this functionality into one single chip.
That is you know, moving to a system on chip where you have all this
functionality, wireless, power regulation, memory, into one single chip.
the other way to do it is the second approach to do this, is to have these
individual chips, which are optimized for their each functionality, and
then you stack them on top of each other using 3D integration.
So, things are moving in both directions more and
more functionality is actually moving into one single chip also.
But there are limitations of what you can integrate
into one single chip, or one system on chip.
Because first of all each of these each of these functionalities
requires a different voltage. They require a different process flow.
For example, a process flow for making NAND flash memory is
very different from a process flow you need for making a logic.
So there are way you can enable them into a one single chip, but it would require
a lot of compromise in your yield. It would complicate your process flow.
So there are limits
to the
amount of integration you can achieve in one single chip using this way.
And especially in mobile space people
are leaning toward integrating these chips using
a 3D package, where you'll use essentially a different process flow for each chip.
So we use a process flow which is optimized for logic.
You use a process flow which is optimized for NAND.
some of
these chips, which are analog chips are
chips.
They could be in fact even made on a 200 mm or a 150 mm fab.
And, so you use what works best for making each of these chips.
And then you finally bring them together and integrate them on top of each other,
or on sideways to each other using this 3D or 2.5D approach.