In March 2023, Nvidia announced a new software library that they call "CuLitho".
Nvidia claims that this computational lithography library can "deliver a performance leap of
up to 40x beyond current lithography".
Most of the comments on the internet have centered on the library's name, which unfortunately
reminds people of a Spanish slang word meaning "small butt".
Butts are funny.
But in this video, we are going to stop touching the "Butt" thing and focus on what this technology
actually does.
So what did Nvidia do that has gotten both ASML and TSMC saying such nice things about
it?
In this brief video, let us dive butt-first into the pool.
## Introducing CuLitho
There was an Nvidia session titled "Accelerating Computational Lithography: Enabling our Electronic
Future" by Dr. Vivek K. Singh.
I think it gives a good overview of the whole situation including some background.
The talk isn't very technical and Dr. Singh seems like a pretty nice guy so I think you
should go watch it.
Dr. Singh describes CuLitho in this way:
> CuLitho is a collection of parallel algorithms invented by Nvidia scientists for accelerated
primitive operations of OPC
He shows a bunch of algorithms whose performance has been accelerated many times over - sometimes
even 100s of times - using GPUs.
These algorithms are integrated into traditional OPC EDA software.
Using parallelism, GPUs can chew through these algorithms far faster than CPUs can.
Speeding these component processes give you an overall faster end to end computational
lithography system - 23-42 times, which is where the headlining number comes from.
And that's pretty much what CuLitho is: GPU-optimized software for more quickly running computational
lithography processes.
But why is it important that we run these things faster?
What is OPC, ILT, and Computational Lithography?
## Lithography
Lithography involves the work of
transferring a chip design from a photomask
onto a resist-coated wafer.
Since the very beginning, we have been using optical lithography.
This is basically a multimillion dollar camera projecting powerful light waves through or
off the mask to transfer a design at high volume.
Up until the late 1990s, the feature sizes printed in a process node were larger than
the light wavelengths used to print them.
This changed with the 180 nanometer node generation, which used the 248 nanometer KrF DUV laser.
Though if you want to talk semantics, the 193 nanometer ArF laser was available then
- but not widely.
Anyway, this situation is bad because when the feature sizes are this small, any deterioration
in the resolution and image quality can cause the pattern to be incorrectly transferred.
And then stuff starts breaking.
## Improving K1
So how are we going to achieve the necessary resolutions with these big, clunky wavelengths?
Let us look at Rayleigh's holy equation once again:
> Resolution = K1 * wavelength / Numerical Aperture or NA
Our options are either to raise NA or lower K1 and those options have tradeoffs.
Raising NA means to collect more light.
It is the concept behind immersion lithography and crazy things like High-NA EUV.
But raising NA also means a thinner depth of focus, which is the vertical distance at
which the image quality is still acceptable.
Depth of focus, as Dr. Singh said in the Nvidia talk makes for cool photographs, but can be
terrible for IC development.
We want that Depth of Focus to be as nice and thick as possible, otherwise the image
is going to blur at a certain depth of the resist.
In that case we need a thinner resist layer, which can cause issues when you get to the
subsequent etch process after lithography is done.
The resist protects the etch acids from breaking through and a thinner resist might compromise
that.
Anyway, so raising NA can be done and is being pursued - but it can only work to a certain
extent.
Thusly the only other thing is to lower the K1.
K1 represents the contribution from the manufacturing process like the resist, the materials, and
the imaging techniques.
This is where computational lithography helps.
It helps lower our k1 and over the years it has helped us lower it by a great deal.
K1 has a physical limit, but we have been trying to get as close to it as possible.
## Computational Lithography
Starting in the early 1970s, we began quantifying the natural principles behind lithography.
This was a difficult task.
Lithography was before then seen as an artisan technique that was highly dependent on an
operator’s individual skill.
But efforts led by IBM’s Dr. Rick Dill and others helped create computer models that
modeled the surface of the resist-coated wafer and how it reacted when struck by light.
Put these principles and others into a computer, and we can then start simulating what happens
when we run light through the optics system, through the photomask, and what is left after
that light hits the wafer.
It took many years for computers to git gud enough to run these simulations, but by the
early 1990s computational lithography had gotten to be useful enough for real world
use.
Now we can leverage our knowledge to improve the printability of a particular chip design.
These tactics are broadly called "Resolution Enhancement Techniques" or RETs.
## RETs & OPCs
RETs are basically little optical tricks that we employ to better transfer the designs over
to the wafer.
Correction, these are nowhere near little tricks actually.
They involve the whole optical system.
For instance, three big RETs introduced over 25 years ago helped bridge the wavelength-feature
size gap at the 180 nanometer node.
They were Phase shifting masks, Off-axis illumination and Optical Proximity Correction or OPC.
I will skip over explaining the first two RETs - though they are very fascinating - to
focus on the third - OPCs.
Optical Proximity Corrections are modifications we make to the chip design layout in order
to compensate for optical distortions.
In other words, we basically mis-print the chip design onto the quartz photomask so that
after the light passes through it, it ends up printing correctly on the resist-coated
wafer.
The first OPCs introduced in the mid-1990s were based on simple geometric rules.
For instance, adding tickmarks at the end of the design lines - kind of like the serif
in serif fonts.
The serif tick mark makes that design line easier to print.
Simple as that.
These simple rules made it easier to check everything at the "Design Rule Checking" stage
at the end of the verification stage.
But because they were so simple, these "rules-based" OPC as they were called were not useful lower
down on the silicon.
So they were used for the metal layer - where the interconnects are - higher up in the IC.
## From Rules to Models
As feature sizes continued to shrink, simple rules no longer cut it.
A new type of OPC emerged called "model-based OPC".
These use extensive computational lithography simulations to correct the entire layout right
before it goes to the fab.
After finishing the design, we get the GDSII file which is almost ready to go to the fab.
We then run this file through the OPC semiconductor design software to add the rules in.
It is impossible for the model to simulate the entire chip design all at once, so it
breaks down the polygons that make up that design into segments and take samples within
those segments.
We then simulate the light's entire journey through the sampled mask segments and even
how the resist reacts when hit by the light.
The program then iteratively makes corrections to the current mask design to optimize for
the proper parameters.
Model-based OPC is very accurate, but its reliance on intense computation and iteration
also means that it can get very slow.
And because the model only takes samples at certain areas of the chip design, we will
still need to run physical verification after OPC.
These long runtimes got longer as chip designs grew more complicated - to the point where
they interfered with development cycles.
## Inverse Lithography
In 1981, Professor B.E.A.
Saleh of the University of Wisconsin-Madison
proposed the concepts of what would eventually be called Inverse Lithography Technology or
ILT.
Like OPC, ILT is a Resolution Enhancement Technique.
The goal is still to improve the resolution of the chip design image transfer.
They just take a different approach.
The flow of traditional OPC operations is from the mask to the resist-coated wafer.
We start with a design and then the simulated model makes slight changes to that design
based on the models' results.
ILT on the other hand goes the other way conceptually, from the wafer to the mask.
We know what pattern we want to put onto the wafer.
What is the best mask design we can come up with to get that pattern - knowing what we
know about how light travels through the lithography machine and interacts with the resist.
Then ILT writes up that whole mask up from scratch pixel by pixel.
This "inverse" approach - starting with the destination and working backwards from there
-
is the key differential from traditional model-based OPC.
Now how do we do it?
Professor Saleh first used a
variant of "simulated annealing", which is a statistical optimization technique that
has popped up a few times before on this channel.
"Simulated annealing" seeks to discover a local optimum.
Saleh first created a randomly generated mask and then made random changes to certain pixels.
"Flipping pixels" as it is called.
Keep what works and drop what does not.
After Saleh's paper, researchers at Berkeley, IBM, and other organizations refined the technique
- experimenting with different methods and results.
In 2003, a startup called Luminescent Technologies made a big splash with their paper,
"Fast Inverse Lithography Technology".
Luminescent gave ILT its present name and strongly pushed it across the industry.
And then there is Intel.
Intel has been funding academic research in the field since the 1990s.
In 2007 they presented their own version of ILT.
In classic Intel fashion they avoided the "ILT" name, calling it pixelated mask technology.
Over time, computational lithography has already added a whole cornucopia of distortions.
But ILT takes it to a new level - these ILT results are very unintuitive like some sort
of horrific mutation of the original design.
And yet the results speak for themselves.
## Bottlenecks
If you look at it purely on the basis of results, ILT takes the cake over model-based OPC.
The masks that come out of ILT tend to be more accurate, have greater fidelity to the
desired pattern, and offer more room for process error.
However, there are also substantial tradeoffs.
First and foremost is computational power and throughput.
Accounting for every pixel in the chip design helps produce a more optimal solution, but
it also means you need a lot of computing power or time.
Some designs could take weeks to process, which is unacceptable.
Second has to do with manufacturing the mask itself.
Today we "write" our photomasks using focused electron beams.
It is slow but precise.
Most masks have what we call Manhattan geometry, meaning that they use shapes made up of many
rectangles.
Masks generated with ILT tend to have more free form to them - with complicated curves
and diagonals.
Masks like these are referred to as curvilinear masks.
Producing these curvilinear masks using the traditional technologies meant that you had
to "fracture" the complex shapes into rectangles, which was challenging.
Manufacturability, computation and competition turned out to be game-breaking issues for
Luminescent and ILT back in the late 2000s and early 2010s.
ILT was just a bit too early for its time.
In a 2016 article for semiengineering.com, former employee Leo Pang recalls that Luminescent
tried to push ILT for the 45 nanometer and 32 nanometer nodes.
But then came 193 nanometer immersion lithography, which improved resolutions to such an extent
that semiconductor manufacturers didn't need to choose ILT over OPS.
While various EDA vendors did adopt ILT into their systems, it was mostly reserved for
special situations and not widely adopted.
In 2012, Luminescent was split up with bits acquired by both equipment-maker KLA and the
EDA-maker Synopsys.
## Changing Times
As I mentioned, ILT arrived a bit early to the party.
But over time the party has caught up.
Mask writing tools improved.
New multi-beam tools like those from the Austria-based IMS now make it possible to produce the shapes
for these complex curvilinear masks in a reasonable time.
However, we still had to deal with the computational challenges.
How can we generate the proper masks without taking too long to do it?
It gets even more daunting when you consider how complex today's leading-edge chips are.
As Dr. Singh mentions in his talk, Hopper has 80 billion transistors on a chip - nearly
double that of its previous generation.
That means trillions of polygons on a single chip.
These ever-increasing demands have forced the fabs to use ILT more and more in their
nodes.
This in turn incentivized them to figure out how to make ILT work faster.
Dr. Singh talks about how TSMC presented intriguing simulation results hinting at how GPUs might
be able to speed up ILT.
Those were just simulations but TSMC wanted to turn those into reality.
Nvidia took up the challenge and the result was CuLitho.
## Conclusion
Techniques like computational lithography have a direct impact on our ability to print
ever smaller features.
It is a massive field with many more functionalities that I have not yet mentioned in this video.
For instance, Source Mask Optimization.
Which is where you optimize both the mask pattern and the illuminating light source
behind said mask to get the best results.
I have always thought there was something a bit funny about how we use computers to
allow us to make chips for faster computers.
Something self-referential about it, I guess.
I look forward to hearing more about the effects and benefits of this software library in the
near future.