Hello, everyone, and welcome to demo session, Implementing
Frequency-Hopping on Xilinx RFSoC
Devices using SoC Blockset.
I'm Bhanu Medasani, Dev Manager at MathWorks.
In the next few minutes, I will cover a brief overview
of the demo, its application areas,
followed by a quick run through of the demo.
Frequency-hopping spread-spectrum techniques
have been widely adopted in space, avionics, military,
and civilian applications.
They have been instrumental in protecting
against jamming and interference,
especially in the [? C4IE ?] applications area
to enable secure communications for mission
critical environments.
Some of the problems we are trying to solve here are--
designing frequency-hopping based applications
require deep knowledge of the underlying hardware capability.
The integration and testing of such applications
are time consuming.
The solution is-- the demo showcases
how you can seamlessly integrate and test frequency-hopping
in your applications targeted for audits of devices.
And the key takeaways of this demonstration are--
SoC Blockset provides, support for frequency-hopping on RFSoC
Devices through the RFDC block.
Through SoC Blockset, you can validate
the frequency-hopping functionality of your system
in simulation, before actual deployment on hardware.
And this example can be used as a reference
for kick-starting designs of frequency-hopping based
applications.
The application areas for this example
are electronic warfare, military communications,
and wireless communications.
And the related industries are aerospace, defense, and CES.
The products used in this example
are SoC Blockset, HDL Coder and the Embedded Coder.
This is a high-level block diagram
of how traditional frequency-hopping is
accomplished.
Here, the processor runs the hopping algorithm
and generates the hop code for each hop interval.
This hop code is then mapped to an appropriate frequency
output of the synthesizer.
The processor configures the synthesizer
at an appropriate time in a slot,
to generate the low frequency for modulating and transmitting
the data.
A similar process is followed in the receive path
to synthesize the known frequency,
to downconvert, demodulate, and decode the data.
This support is enabling RFSoC devices
through the real-time ports.
There are a set of resistors and status
lines available to configure the NCO frequency.
These ports can be configured in real-time,
directly from [? PL ?] when compared to the software
configuration through RF tool, from the [? PS. ?] This level
of tight coupling enables users to achieve high hopping rates
when compared to traditional mechanisms.
SoC Blockset provides Adaptive Data Converter
block as part of its library.
This block supports modeling a simulation of data path,
and generation support for Multi Tile Sync, Real-Time Ports
for NCO, and [? agency ?] control for all generations
of RFSoC devices.
The real-time ports for both adcs and dacs
are available in the Advanced tab of the RFDC block.
There is also a Testbench block which can simulate the behavior
of the DAC [? bot. ?] Using this blocked output spectrum
of the transmitter [? bot ?] can be visualized in simulation.
The slide depicts the high-level architecture
of a typical FH system.
The Frequency-Hopping DUT sits in FPGA,
and consists of a Frequency-Hopping Controller,
Transmitter, and Receiver Subsystems.
The hopping controller can be configured for high frequency,
range, and step.
It also provides the hop signals,
like frequency and timing information,
to the transmitter and receiver subsystems.
That transmit subsystem consists of transmit algorithm,
which is a tone generator whose output samples are
fed to the RFDC block through the FH Tx interface.
Similarly, in the receiver [? bot, ?]
when the samples from the RF data converter
are received through the FH Rx interface
and fed to the receiver algorithm.
The processor algorithm reads and processes the data,
and outputs sent to host.
In this model the loopback data, or the tone samples,
are sent to host for visualization.
Here, we can see the final integrated top model
for the Frequency-Hopping application.
The top model consists of the processor, FPGA subsystems,
memory interconnect, and the RFPC block.
There is also a Testbench block which can simulate the behavior
of the DAC [? bot ?] and help in visualizing the output spectrum
of the tramsmit [? bot. ?]
The FPGA model consists of the Frequency-Hopping DUT.
The DUT consists of a Frequency-Hopping controller,
Transmitter, and the Receiver subsystems.
The hopping controller can be configured
for high-frequency range and step.
It also provides the hop signals,
like frequency and timing, to the Transmitter and Receiver
subsystems.
The Processor model consists of a DataReadTask,
used to read the output of the FPGA algorithm.
This data is then passed to the spectrum scope,
through the external mode interface, for visualization.
Now we can simulate the top model,
and visualize the signals at a system level,
and verify the functionality.
Here, we can observe the frequency-hopping happening
in the simulation mode, at the output of the DAC,
as per the Configure, Operate, and Hop Step Frequency.
We can also monitor the spectrum scope on the processor output,
to confirm that the receiver is also hopping, and is
in sync with the transmitter.
Using a SoC Builder, you can generate the bitstream
and the software executable for the model
to run in External or Deployment mode.
Alternately, you can use the prebuilt [? BIT ?] files
and the software executable, which
are provided as part of the example Run in External Mode.
Once deployed on hardware, you can monitor the receiver tone
on the spectrum scope in the Processor model.
As you can see, the output is a stable 1 megahertz tone,
indicating that both transmitter and receiver
are hopping at the same frequency,
and are in time sync.