[Slide 1] Okay welcome back, we're at the
end of week three and what I'd like
to do in this final lecture is to
take the ballistic model that we've developed and
compare it against an actual device, a couple
of devices actually, to try to determine how
close to the ballistic limit modern day transistors
operate. It will also give us an example
of how you apply this theory to measure
device characteristics. [Slide 2] Just by way of
quick review, we developed a theory for the
ballistic MOSFET, we did it by way of
Maxwell Boltzmann statistics because things were simple then,
so we have simple expressions for the linear
and for the saturated region currents. [Slide 3]
We have more complicated versions of the same
IV characteristic that apply for Fermi-Dirac statistics and
when we need to, we can evaluate those
as well. [Slide 4] So the question we're
dealing with in lecture six of week three
is how close to the ballistic limit do
modern MOSFETs operate? [Slide 5] So let's take
a recent MOSFET for which we have some
data. This is a device that has some
key parameters are here. The oxide is not
quite as thin as it is in the
transistors today. It has a polysilicon gate, it
has a drain voltage 1.2 volts. This particular
device didn't intentionally use strain, so it hasn't
got quite as high currents as you would
see in the most recent devices. All the
measurements were done at room temperature and the
particular device that we will look at had
a physical channel length that was determined by
a scanning electron microscope to be 60 nm
long. [Slide 6] So this is the device
that we'll take a look at. Here are
the measured IV characteristics, and I'll note that
the on current is about 800 microamps per
micrometer of width. They said if you use
strained silicon, you'll tend to get higher on
currents than this, and if you slightly thinner
gate oxide insulators, you'll also get a little
bit higher on currents, but this is a
good on current for us. If we look
at the slope under highest VDS in the
VDS regime, that's the total resistance between the
source and drain, and that's the sum of
a channel resistance and whatever series resistance is
there. So we can just look at that
slope and take one over the slope, since
we're taking voltage divided by current per micrometer,
we express the resistance as 435 ohm micrometers.
So if we have a 1 micrometer wide
MOSFET, the resistance is 435, if we have
a 2 micrometer thick MOSFET, the resistant is
half of that. [Slide 7] If we look
at the transfer characteristics under low and high
VDS, then we could deduce for example, a
threshold voltage in the saturated regime VT set.
In this particular device it's about .42 volts,
so that's a relatively high threshold voltage and
that's one of the reasons that the on
current is a little bit lower than you'll
see in the highest performance devices, but this
would be a low leakage device, it would
have a low off current. [Slide 8] So
we can see that here. If we look
at the transfer characteristics of this device on
a long plot, low VD, high VD, we
can look at the off current and the
off current is actually pretty low, five nano
amps per micrometer of width. The subthreshold swing
we just deduce that from the slope here
is 81 mcolts per decade, which is a
good subthreshold swing, and there's no reason that
the DIBL in the sub threshold swing need
to be the same numerical value, but they
happen to be in this case, so the
DIBL is also a good value, less than
100 millivolts per volt, so it's a well
behaved transistor. [Slide 9] Now when we're analyzing
this device, we're going to have to be
careful about series resistance. Remember our theory is
expressed in terms of the voltages that actually
get into the heart of device, but between
the heart of the device and the contacts,
there are these extra series resistances and we
have to account for that. [Slide 10] So,
let's look at the on current first and
see if we can deduce what the injection
velocity is in this particular device. So the
on current was 800 microamps per micrometer. Now
the series resistance for this device was independently
measured and it was measured at 220 ohm
micrometers, so that is a fixed series resistance
that's attached to the device and we have
to subtract that out or account for it.
That means that if I'm looking at on
current conditions, I'm applying 1.2 volts to the
gate terminal, and I have a on current
of 800 microamps per micrometer, but I have
a voltage drop across the series resistance, which
is half of this total here, 110 ohms.
That means that the actual gate to source
voltage between the intrinsic terminals is a little
bit less than 1.2, it's 1.11, so I
need to account for that. The measured gate
inversion layer capacitance, or the measured gate capacitance
under strong inversion conditions is 1.55 microferads per
centimeter squared, and now I can deduce the
charge at the top of the barrier since
I know the gate to source voltage on
the internal terminals we've estimated the threshold voltages
and saturation, we measured the gate capacitance. And
I could take that value I could divide
it by q charge on an electron to
determine the number of electrons per square centimeter
in the channel under these conditions, and it
turned out to be 6.7 times 10 to
the 12th per square centimeter. Okay, so that's
the analysis, now we know that on current
is related to average velocity at the top
of the barrier, and we know that we
have deduced the charge at the top of
the barrier. So we can take this result,
we can take the measured on current, and
we can deduce the average velocity at the
top of the barrier, and what we find
is that it is .75 times 10 to
the 7th centimeters per second, and now our
question is how close is this value to
the ballistic limit? That's what we're trying to
determine. [Slide 11] So we go back to
our calculation. The ballistic injection velocity is this
unidirectional thermal velocity 1.2 times10 to the 7th
centimeters per second multiplied by a ratio of
Fermi-Dirac integrals that increase that average velocity above
threshold. While we know the inversion layer density,
we've estimated that, so we can look here
on this plot inversion layer density of 6.7
times 10 to the 12th, we would expect
a ballistic injection velocity of 1.9 times 10
to the 7th centimeters per second. We know
the actual velocity, so we could estimate the
ballistic ratio. The on currents are proportional to
the velocities, so the ballistic ratio then, or
the ratio of the measured on current to
the ballistic on current is just a ratio
of these two velocities. [Slide 12] And what
we find from that calculation is that this
device delivers 40 percent of the ballistic on
current. So that's relatively close, close enough that
we have to be aware of this ballistic
limit and think about it. As I mention
this particular device was designed more for low
leakage and not for maximum on current, so
you'll find in transistors that are designed for
maximum on current, that this number is little
above 50 percent, even 60 percent or so.
So, we're within spitting distance of the ballistic
limit. It's something that we need to be
aware of and think about. Now what about
the linear regime? We could take a little
closer look at that as well. [Slide 13]
So if I look at that linear regime
and I just take this slope of the
current there, that's my total resistance between the
drain and the source terminals and that resistance
was 435 ohm micrometers. Now that total resistance
is the sum of the actual resistance of
the channel plus the series resistance, and the
series resistance was separately measured to be 220
ohm micrometers. So our channel resistance itself is
215 ohm micrometers. Now under these conditions we're
operating at lower currents, so the internal voltage
is very close to the external voltage that
was applied. Let's assume that the channel inversion
charge is close to what it was before.
DIBL was low so we can account for
that, and the result is that I could
take these numbers and I could do this
calculation. I can deduce from the inversion layer
density the location of the Fermi level. I
know the inversion layer charge. I could deduce
what the ballistic channel resistance would be, and
what you'll find is that the ballistic channel
resistance is roughly 60 ohm micrometers. So the
measured, if I think in terms of conductance
take one over these, the measured channel conductance
is less than a third, less than .3,
of the ballistic channel conductance. [Slide 14] So
what we've concluded here is that if I
look at the ratio of the linear current
to the ballistic linear current, that's about .3.
If I look at the ratio of the
high voltage on current to the ballistic on
current, that's about .4. So one of the
messages is, and this is a little bit
surprising, is that transistors operate closer to the
ballistic limit under high-drain bias than they do
under low-drain bias. Now that's just the opposite
of what you might've thought, because under high
voltage, carriers have a lot of energy and
they can scatter more, so that's something that
we're going to have to try to explain
when we get to next week and discuss
scattering in more detail. [Slide 15] Alright, now
I want to turn to another comparison. This
is an extremely thin SOI device fabricated at
IBM. In this case, rather than doing the
analysis from the major data, I'm going to
do it a little more differently. We're going
to do a fully quantum mechanical simulation of
this structure in the ballistic limit using a
simulation tool on a nanohub that treats the
quantum transport of electrons under ballistic conditions self
consistently with the Poisson equation, and we're going
to compare that simulation to the measured result,
and see if we can determine how close
to the ballistic limit we are. [Slide 16]
Here are the results. This is a 40
nm channel length extremely thin SOI device. The
red lines are the simulated results including the
measured series resistance for this device. The blue
dots are the actual measured results and what
you'll see it's a little bit hard to
see the linear regime because you have to
separate out the contact of the series resistance,
but the ratio of the linear current to
the ballistic linear current is about .2 in
this case. The ratio of the ballistic on
current or the actual on current to the
ballistic on current is about .6 in this
case. It's a little bit higher performance device.
So again, you'll see the basic message is
that silicon MOSFETs deliver roughly one half of
the ballistic limit on current, and it's interesting
that that's been similar for about 15 years.
You might ask why is that, if you
do this kind of analysis, and you know
we did have many years ago on 250
nm channel length devices, you would find even
at that time, the devices were delivering about
half the ballistic on current. Now we're at
40 nm channel length and we're still at
roughly half, just a little bit higher. You
know why is it stuck at about half
or so. And a lot of that has
to do with the need for well-tempered MOSFETs
that are electrostatically well-designed. If I were to
look at a device on this technology that
had a 30 nm channel length, it would
operate closer to the ballistic limit, but it
would have a sub threshold swing and a
DIBL and things that make it not as
well-tempered a MOFSFET. So what happens in each
technology generation is that you reduce the channel
length, which would allow you to operate closer
to the ballistic limit, but then you do
things like thin the oxide which introduces more
surface roughness scattering, raise the doping in the
channel which increases more scattering. The things you
do to make the device electrostatically well-controlled end
up introducing more scattering, and at the end
of the day when you're all done, you're
back to about half of the ballistic limit.
So that's something that has been very tough
to get around in silicon MOSETs. It's just
hard to get more than about 50 or
60 percent of the ballistic on current. The
other very interesting thing from these analyses is,
you operate closer to the ballistic limit under
high voltage than you do under low voltage,
and that's something that at first glance doesn't
appear to be right, requires some explanation, and
there is a very simple explanation that will
discuss next week. [Slide 17] Now, what about
3-5 transistors? You know, there are 3-5 transistors
that operate in ways that are similar to
MOSFETs, controlling potential energy barriers. What would happen
in a 3-5 MOSFET? Well, let's compare by
looking at silicon, where the motilities tend to
be roughly 250 cm squared per volt second.
We know the effective math, we can compute
the unidirectional thermal velocity, we can deduce the
ballistic velocity and we find that even at
40 nanometers, the ballistic mobility is significantly larger
than the real mobility, which means that the
device is not operating close to the ballistic
limit, maybe in this quasi-ballistic limit. Now let's
look at the same thing for an Indium-rich
in-gas transistor called a hempt. Now this is
a very different kind of device where the
interfaces between these layers are grown with lattice-matched
epitaxy and are atomically flat. We don't have
the rough scattering that we do in a
silicon dioxide silicon interface. The motilities can be
very high on the order of 10,000 cm
squared per volt second. Now you might think
that wow, I would get an enormous boost
in current because the mobility is so much
higher. Well let's look at this. One of
the reasons tjat the mobility is so high
is that the effective mass is quite low.
We can compute the unidirectional thermal velocity. It's
almost double that of silicon, but we can
also deduce the ballistic mobility, and when we
deduce the ballistic mobility, we can see that
it is considerably lower than the actual mobility.
So for a 3-5 transistor like this, we
would expect the ballistic mobility to be limiting
the current, not the real mobility and we
would expect these devices to be operating very
close to the ballistic limit. So silicon operates
well below the ballistic moment, but our expectation
is that 3-5 amps or high-performance transistors should
operate well above the ballistic limit. [Slide 18]
So here's an example. These are some high-performance
devices that were built in Professor Dale Heso's
lab at MIT two years ago. These are
40 nm channel links here you can see
the indium-gallium-arsenide channel and various wideband gap layers
on top of it, a shockey barrier gate.
We won't go into the physics of this
but I'll just tell you at this time
that it operates by manipulating potential energy barriers
just the way that a MOSFET does. Now
here are measured and simulated results. So again,
we did a numerical simulation of this device
with a quantum model, that's not so important
because there aren't a lot of quantum mechanical
effects going on this device, but it was
a ballistic model also, and one was done
self-consistently with the Poisson equation. The red lines
are the ballistic simulations. The blue dots are
the measured results. The ballistic simulations include the
measured series resistance of this device and what
you will notice is that this device is
operating much closer to the ballistic limit, in
fact, quite close, about 85 percent of the
ballistic limit or so. So modern-day high-performance 3-5
transistors are indeed operating very close to the
ballistic limit just as you would expect. [Slide
19] Okay, so we can wrap up week
three and wrap up this lecture in particular
by reminding you of the key points that
silicon MOSFETs operate at about half the ballistic
limit. 3-5 MOSFETs operate close to the ballistic
limit. Now if we want to understand these
issues about why are we below the ballistic
limit, why only half in one case and
almost at the ballistic limit in the other
case? Why do we operate closer to the
ballistic limit under high-voltage and under low-voltage? In
order to understand the answers to those questions,
we need to understand scattering in more detail.
So that's our focus in week four. We
will look at scattering and transmission. We'll apply
it to the MOSFET again, and then will
be able to understand some of these questions.
So thank you for sticking with me in
week three and I'll look forward to seeing
you in week four.