So the two approaches I just described you for making
FinFETs, both the subtractive approach and the replacement of
fin approach were I demonstrated them on a bulk substrate,
but you can also made FinFETs on these SOI substrates.
so I will describe to you a process
flow to make SOI FinFETs and what you do
is you start first of all their starting point is this SOI wafer so you have this
thin silicon fin which has a thickness, a
predefined thickness which you'll get from your SOI vendor.
And this and then you have this oxide layer or this box layer
which separates the silicon, thin silicon from your silicon substrate.
And then again what you can do is you can have your spacer and your hard
mask and you can pattern those in here. And then what you do is you
pattern these pattern this silicon or SOI substrate.
And what you are left with are essentially fin,
which are now standing on top of your oxide.
So you are left with these fins and they are standing on this
oxide layer. A key difference between this
process and the process flow that we did before is
that this height of this FinFET device. The height of my
fin in my height of my fin is determined
by the thickness of the silicon that I started with.
So in the other cases we saw that your height was determined by the etch back but since we started from SOI wafer with a predetermined silicon thickness, the height of my fin in this SOI FinFET
is fixed by, this, height of the substrate that I started with.
Which is, in a way good, because whenever we do a etch step to
determine the height of my, fin, I'll be having additional
variability coming into a picture do to the uniformity of the, etch process
But, in, this case of an
SOI, FinFET, my, variation in, height would be negligible because it, assuming
that I had a good uniform, silicon substrate, SOI substrate to start with.
There's some more additional advantage that you, get from,
you're, doing a SOI, FinFet, kind of, process flow.
And I'm using this,
cartoon from, Synopsys, to demonstrate, this
additional, improvement so you get an additional
improvement in your, electrostatics, in your,
in your, sub-threshold slope, in your, DIBL
From, going from a bulk to a SOI FinFET process flow.
So as we discussed earlier, going to, going to
a FinFET process flow, you get very good gate control, so you have this.
Fin and I've essentially taken apart it along this direction, along the
fin, parallel to the fin direction, and my gate would be wrapping around this fin.
So I have very good electrostatic in this
region where my gate is wrapping around this fin.
But what about this region which is below?
So, in below, I don't have my
gate wrapping around this substrate below my fin.
So my source can still talk to my drain in this region below.
So this region below still not control my, my gate.
But if I do this SOI, FinFET kind of a process flow.
I remove this substrate below and replace it
with this oxide.
So, I further improve my electrostatic, I further
eliminate my talk between my source and drain.
And I get a even better electrostatic when I go from a bulk to SOI - FinFET flow.
But there's some additional challenges and I'll, I'll talk to you about
those later going when we compare SOI versus bulk FinFET in class.
So, hopefully, you know, I have shown you
a couple of, approaches to make, this FinFET, pattern.
These, fins for making our FinFET transistors, so
the question we ask is what happened to
all these, implant steps and these isolation steps
that we used to do in planar devices.
So I, I describe to you earlier when we, talked about the, process
flow.
For front end of the line we use these well
implants to isolate, or to define the regions where we'll be
growing our, we'll be making our pMOS and nMOS
devices so we define this P Well region and these N Well region.
To you know, define the regions were we make the
pMOS and nMOS So how, the question is, how do I do that
in a Fin FET device. So the
answer is that you can do it two ways So you can have when,
after we are done defining these fins we can
again, you know come back. And, what we can do is cover our
fins where we want to make our P well, so
we cover the rest of these fins by a photo resist.
And what I can do is then come and do and do a
implant step over here, so I want to make a P well over here, so I can do this boron
implant, and I can define my P well region.
So what this, is this the only way. probably not. We could do
something smarter. So what we can do is before we start to
make these make these fins, what we can do is we can pre-implant our substrate.
So we can implant our p-well.
And we can implant our n-well before we start to pattern these fins, and then
we can pattern. We can take that and we can essentially
pattern these after we pattern these fins we automatically have these
p-wells and n-wells defined. So we kind of avoid
this damage which could have been created in this case
by this implanting these small and
delicate and narrow fins.
And we have these p-wells and n-wells built into our fin devices.
Another thing which is unique to this FinFET process flow, and I
want to talk to you a little bit about as to how to achieve isolation between,
this Our P mos and our N mos devices.
So when we talk about planar planar devices.
I described to you this process flow called shadow trench isolation.
Which is used to isolate between our pMOS and our nMOS
devices. So if we have our pMOS and nMOS adjacent
to each other, they might have this phenomenon called, latch
up and to avoid that we essentially want to isolate our p-mos
and n-mos regions and the way I
described to you earlier. we achieve that is to do this
process flow called shadow trench isolation where we Etch
this trench into our, we etch this trench, which
separates our PMOS, our p-well, and our
n-well regions, and we fill it up with an oxide and planarize
it, and that essentially isolates. So, and avoids any crosstalk between
our p well and n well. So how do we achieve that in in this guy?
How do we achieve that in our in our Fin FET devices?
So, the question is how do we achieve isolation in Fin FET device.
So if you just look at this if you
just look at this picture you have these trenches into which you have a failure.
Sorry let me use the color of oxide.
So you have all these trenches into which you have filled oxide and then you etch
them back to reveal uh,your the fin your given height.
So you have these silicon fins which are embedded between these oxide trenches.
So if you think about it you know, you already have these trenches or these STI
structure or isolation built into your FinFET device.
So I will show you one approach were you know, you can achieve your isolation
between your P Mos and your N Mos
devices without doing too much of extra processing.
So let's say, shown here is this two fins which are of n
mos, and these are two fins which are of p mos kind of transistors.
And you could have these source drain, n plus
source drain for n mos, p plus source drain for
p mos, and you can, what you need then
is this, p well region, and this n well region.
And shown here is one approach
where as long as I contain my n well region within this within this
height of my etched silicon. I can easily achieve this
STI isolation without requiring anymore extra steps.
So in this case you can see this isolate, this p
mos and the n mos region are isolated already from these
by using this etch that we use to define, the
define the silicon fins. So this is not the only approach and
there could be many possible approaches but it just depends upon your creativity.
And you can be assured that we will test that in one of
the problem sets or a, one of the one of the exams to other
approaches that you you can use to achieve isolation.
But shown here is essentially that since it's a fin you have these long trenches or long
silicon fins you can build into, you can build your isolation into your fins.
So
certain
process flow process has become easier.
There are a lot more process steps which have become hard, and I talk about those in
the next video as we move from a planar to a Fin FET device.