Now let's focus on the hardware implementing cache
coherence entirely in addition to giving the shared
address space. There are two possibilities if the
hardware is going to maintain the cache coherence. One
possibility is what is called write invalidate scheme.
And here the idea is, if a particular
memory location is contained in all the caches,
all these processes have fetched this particular memory location
Y, and it's been sitting in the private
caches of all these processes. And if now,
process of P one, decides to write to
this particular memory location it changes to from y
to y prime. When that happens, what we're
going to do is, the hardware is going to ensure that
all of these caches are invalidated. So, the
way it's done is that the hardware, as soon
as this change happens, is going to broadcast a
signal on the bus. Called invaldidate memeory location Y.
So that's something that propagates on the system bus,
and all these process of caches, are observing the
caches, and this is sometimes referred to as snoopy
caches, in a, in a lighter vein, these caches
are snooping on the bus to see if there's
any change to memory locations that are cached locally.
And in this case, if an invalidation signal goes out
for a particular memory location y, then each of these caches
are going to say do I have that particular memory
location? If I do, let me invalidate it. So, that particular
memory location gets invalidated. So the idea is if you
have that particular memory location, invalidate it. If you don't have
that memory location, ignore it. Right? So if you don't
have it, you don't have to bother, but if you particularly
happen to have this memory location cached in your
private cache, and if you observe an invalidation for
that particular memory location, you go ahead and invalidate
it. That's what is called write invalidate cache coherence
scheme. You may already be one step ahead of
me, and you may be thinking what would be
an alternative to doing this invalidation? And, and you
may be, you may be right. You thought of perhaps
updating the caches. That's what is called write update
scheme. The idea here is, if this guy is going to
write to this particular memory location, modify to y
prime, what we do is, instead of invalidating it on
the bus, if there is a capability in hardware
to send an update for this particular memory location on,
on the bus. You send it out saying that
I modified this particular memory location, this is a new
value, and if these caches happen to have the same
memory location, they all modify it from y to y prime.
And now, all of these caches have the new value
of y and the old values disappear from the system. So
in this case, what we are doing is, if you
have it, update it. Once again, you're snooping on the bus.
Each of these process of caches is snooping on the bus
and if they see an update for a particular memory location,
they're saying, well, let me modify it so that
future accesses by my CPU will get the most
recent value that had been written into this particular
cache line. That's the idea behind write update scheme.
Now whether we're talking about write update scheme or
the earlier write invalidate scheme, one thing should become
very clear in your mind and that is there
is work to be done whenever you change some
memory location that could conceivably be cached in the
other private caches of the CPUs. And the invalidate
scheme has sent out an invalidate message. If it's
an update scheme, it sends out an update message. And
that kind of transaction that's going on is, is
an overhead. And as, as a system designer, one
of the thing that we've been emphasizing all along
is that we want to keep the overhead to a minimum.
But you can also see immediately that the overhead is going to be something
that grows as you increase the number
of processors. As you change this inter-connection
network from a simple bus to a more exotic network. And also depending on
the amount of sharing that is happening for a particular shared memory location.