Computer chipmakers are adding more "cores," or processing units for increasing the computational
power.
But, the problem of communication between cores becomes bigger when the computer chip
has more cores or processing units.
For years, a Singapore Research Professor at MIT, has argued that the massively multicore
chips of the future will need to resemble little Internets, where each core has an associated
router, and data travels between cores in packets of fixed size.
This week, at the International Symposium on Computer Architecture, the MIT researchers
unveiled a 36-core chip that features just such a "network-on-chip." In addition to implementing
many of the group's earlier ideas, it also solves one of the problems that has given
troubles for the previous attempts to design networks-on-chip: maintaining cache coherence,
or ensuring that cores' locally stored copies of globally accessible data remain up to date.
The researchers named their chip as SCORPIO. This new 36-core chip is "tiled," meaning
that it simply repeats the same circuit layout 36 times. Tiling makes multicore chips much
easier to design.
In today's chips, all the cores — typically somewhere between two and six — are connected
by a single wire, called a bus. When two cores need to communicate, they're granted exclusive
access to the bus.
But that approach won't work as the core count increases: The Cores will spend all their
time waiting for the bus to free up, rather than performing computations.
In a network-on-chip, each core is connected only to those immediately adjacent to it,
and it will provide multiple paths for any destination.
However, One advantage of a bus, is that it makes it easier to maintain cache coherence.
Every core on a chip has its own cache, a local, high-speed memory bank in which it
stores frequently used data.
As it performs computations, it updates the data in its cache, and every so often, it
undertakes the relatively time-consuming task of shipping the data back to main memory.
But what happens if another core needs the data before it's been shipped? Most chips
address this question with a protocol called "snoopy," because it involves snooping on
other cores' communications. When a core needs a particular chunk of data, it broadcasts
a request to all the other cores, and whichever one has the data ships it back.
If all the cores share a bus, then when one of them receives a data request, it knows
that it's the most recent request that's been issued. Similarly, when the requesting core
gets data back, it knows that it's the most recent version of the data.
But in a network-on-chip, data is flying everywhere, and packets will frequently arrive at different
cores in different sequences. The implicit ordering, that the snoopy protocol relies
on, breaks down.
The MIT researchers solve this problem by equipping their chips with a second network,
which shadows the first. The circuits connected to this network are very simple: All they
can do is, declare that their associated cores have sent requests for data over the main
network. But precisely because those declarations are so simple, nodes in the shadow network
can combine them and pass them on without delays.
After testing the prototype chips, to ensure that they're operational, the researchers
intend to load them with a version of the Linux operating system, modified to run on
36 cores, and evaluate the performance of real applications, to determine the accuracy
of the theoretical projections. At that point, they plan to release the blueprints for the
chip, written in the hardware description language Verilog, as open-source code.