Now that we have formed our transistors and activated the implants and formed
silicide the next thing we do is, essentially give it,
give this lot to the back end of the line guys
And then their job is to deposit all the interconnect layers and
form the contacts and complete the rest of the process fiow.
So the first thing that that the back end of the
line process guys needs to do is form a contact plug.
That is how to contact these transistors that we just formed. So the first thing they do is they etch this hole into the oxide. So this is the oxide layer.
So they etch this contact hole, and then the first
layer they deposit is actually a titanium layer, that they deposit
just
titanium layer over here.
This titanium layer, the purpose of that it's gettering layer, so it it
getters all the oxygen that was you know, left at the surface.
And then oxygen which was, produced on the surface
during this etch, and it helps in lowering the contact
resistivity
Then the second there, they deposit the conformal Ti-nitride layer.
So they deposit conformal Ti-nitridue everywhere.
And this Ti-nitride acts as a, acts as a barrier material.
So what this trinitride does is it acts as a barrier material.
So this trinitride layer it prevents, it acts as a barrier,
so whatever metal we fill over here, the metal that we
stops the rain. Stunts them from diffusing it into oxide
Also Tungsten uses this precursor with is Tungsten hexa-fluoride
So which has a high reactivity with both oxygen in the oxide
and also with the titanium below.
So this this this barrier layer essentially
prevents that precursor from reacting with this outside
and the silicide
and also it prevents the metal from diffusing into the oxide
So once you deposit this
Ti-nitride layer. Then you do
a CVD deposition of Tungsten. So this Tungsten is a CVD deposition.
It starts its conformal CVD deposition. It starts depositing from both
sides and then it starts growing
and then it starts filling it up with tungsten.
And you fill it up from both the sidewalls and you,
you keep filling up until they meet in the, the middle and then often the seem
forms because it's a CVD process. So there's a seem formed in the tungsten.
So these are the different process flow
process steps involved in making this tungsten plug.
Let me show this in 3D.
So the first thing we do is we start with our nice.
Wafer that the front end of the line gave to us and then we cover
it with a photoresist, it's covered with a photoresist and then
you pattern these holes. So you pattern these holes, which will be
acting as the contact plugs and then you etch those holes into the oxide.
So you etch those holes into the oxide so you can see these holes
which are etched into the oxide.
The next thing you do is you fill it up with titanium over here.
So you, you deposit, you sputter
a very thin layer of titanium. And then you deposit this Ti-nitride seed.
So this Ti nitride seed, you know, either using CVD or ALD
kind of a process, because you want it to be very conformal.
So you deposit this conformal Ti nitride seed and it fills
everywhere.
And then the next step you do is you do a CVD, the deposition of your tungsten so
the next thing you do is your CVD of your tungsten which is your plug material.
Again, it's a CVD process, so it goes from
both these sidewalls and you can see it leaves this
seam in the middle
and and then you, the next thing you do is you polish it off.
So you polish off this extra tungsten on the top.
You have to polish off this, tinitride barrier layer
in there.
And what you're left with are these nice plugs which are now filled with tungsten.
The
next set of module the, in your back end of
the line process flow, once you have, done making the, once.
you have done making the plug
So
once you have made these Tungsten plugs
which connect to your transistors
the next, the next big module is making these
interconnect lines. That is making
these
different levels of interconnect which route the signals
between your different transistors
between your different cores in your micro-processor.
in your micro processes. So as I described to you earlier,
Modern day
microprocessor has anywhere between 9 to 10 levels of these interconnects
And the ones which are at the very bottom, they're called as local interconnects.
Because they run across short distances.
So they just connect nearby transistors and nearby SRAM cells
The one on the very top are thick lines
then they are called global interconnects and
they typically route the signals between the
different cores
in your microprocessor. And the one in the middle are called
intermediate. intermediate levels of
interconnects
And for all these levels of
interconnects
universal equation which determines the delay is that
the delay for any of these levels of
interconnects
is proportional to the resistance of this metal line
Proportional to the resistance of this metal line
And it's also proportional to the capacitance
So it's proportional to the capacitance that this line has.
So this line has with it's adjacent line and what
it has with the line at the top and the bottom.
So if you need to minimize the delay so one of the main requirements from the
device dies of the circuit dies if you minimize the delay.
So there are only two variables that we can play with.
We can play to reduce the resistance of this line
and we can play to reduce the capacitance of this line.
So let's look at how do we reduce the capacitance.
So I want to look at from a
material perspective how we can reduce the capacitance.
The capacitance between these
interconnect lines is can be described by this simple equation.
Where it's proportional to the height and it
is inversely proportional to the resistance between these interconnects.
So one thing we can play around is with the layout.
So we can make these interconnects Shorter, and we can separate them
with more distance, and that's one way to change
to influence this capacity.
But from a material perspective, what we can do is, we can lower the
k
of the dilectric.
So, we can lower the k of the dielectric which is separating these two metal lines
and that, that is one way we can lower this capacitance.
So there are multiple ways you can try to lower the k.
One way is to reduce the density of your silicone oxide.
.
So silicone oxide is, is the lowest scale material.
That, we know it has a dialectric constant, or k of 3.9.
So, one way you can do is take this silicone oxide and try to make it porous.
Or try to reduce its, density to reduce its k value.
The other way it can be attempted is to reduce the polarization, or
reduce the density
of silicon oxide by incorporating other elements into
it. So the one way we can lower, so the k
value, or the dielectric constant, is proportional to the amount of.
Is proportional to the polarizability of the bond so silicon
oxygen has that bond is very polar one way we can reduce the
polarization is by introducing carbon so the carbon -oxygen bond has a much lower
ability and so one way is to reduce the
ks that people introduce other elements into the silicon oxide.
So they introduce fluorine and that lowers that gives you some reduction in k.
It reduces your k to 3.7. more importantly and more
importantly and more pervasively
is what is used as you in, introduce these methyl groups.
So you introduce a carbon into your
film, and that reduces your k value substantially.
It reduces your k to 2.8, and that is that is also, it, it's used
pretty pervasively
in the industry.
the other way you can reduce the k is, the ultimate way to reduce the kis
to use air. So, the silicon oxide as I just
described has a
K of 3.9 or 4. Air has a k or dielectric constant of 1,
and people have What, how they introduce this
air in in this back end of the line flow is by introducing these air gaps.
And in one of the homework problems, we will discuss how
to, how the different ways we can introduced air gap.
But shown here is this picture.
so these are the two metal lines.
And you have you have air gap between them.
So this region is essentially air and
that reduces the capacitance between these two metal
lines
and this is also used used regularly
in the industry especially applications chips involving memory.
Such as flash that has a very regular pattern of
lines that has a very regular pattern of lines interconnect lines.
bit lines and word lines and air gaps is is used routinely to reduce
the, reduce the capacitance between these middle line and
also to reduce the capacitance between neighboring cell in a flash
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