Okay. So now that we have seen a little example of
how the ROB-based processor works, let's look at a ROB timing example. So this
is how we can figure out what happens when without actually tracking everything,
like in the previous, very busy video. Here we have some instructions.
Here we have what latencies of various units are.
And now we're just going to track when instructions are issued,
when they begin executing, when do they write the result, broadcast it, and
when do they commit. And here we will put some comments that kind of, you know,
help us tell what happened when and
why. This time, let's make it a bit different from before. First,
our processor will free our reservation station when the result is broadcast,
not when we actually dispatch the instruction. This can happen for
example, because a processor is doing something speculative and
it wants to keep the instruction until it's really sure that you know,
the instructions should have executed. So some of the processors actually do
this. So, let's try an example with this. The processor can still issue,
capture a result and dispatch the instruction in the same cycle. But
the execution will again happen in the following cycle. This is just like
the previous processors. And again, we have the add take one cycle,
the multiplication takes ten cycles and divide takes 40 cycles.
So let's see. Well, in cycle one, we will try to issue the first instruction and
nothing else can happen because we do not have any other instructions in
the processor. This instruction, of course, being the first one that we know
does not depend on anything, so it will being executing in the second cycle.
It is a divide instructions, it takes 40 cycles to do it.
So, 40 cycles after this one, we will try to write the result, and
that happens in cycle 42. And commit will happen in the following cycle,
because this is the very first instruction, so we can just say 43 here.
Now let's go to this multiplication. Once we have some instructions in
the processor, we have to start worrying about reservation stations and
ROB entries and so on, and we haven't said how many ROB entries we have, but
let's say we have a lot of ROB entries. However, we still have two divide
multiply reservation stations and three add subtract reservations stations.
So now, one of our reservation stations for divide and
multiply is busy between cycles one and 42. There is, however,
another one so this multiplication can be issued in the following cycle. So
it will issue in cycle two. When can it execute? Well, it uses R5 and R6.
This doesn't use R3, so it can actually execute in the very following cycle.
So we will star executing it here, takes ten cycles, so
it will broadcast the result in cycle 13. And when will we commit?
Well, we cannot commit in cycle 14. Now, we have to wait for
both the previous instruction to commit N for us to have a result, so
really we will commit in cycle 44. Now let's look at this add here.
It's using R7 and R8, so it will be executing right after it issues.
We have ADDand subtract reservation stations, remember we have
three separate reservation stations for that. So we will issue in cycle three,
start execution in cycle four, takes only one cycle so we will write the result
in cycle five, and now when do we commit this instruction in cycle 45.
Now things become a little bit more interesting because this multiplication.
Wants to issue in cycle four. Remember we are issuing instructions in order,
we have reached this instruction in cycle four, we want to issue it. However,
we need a multiplication and divide reservation station for that. And we free
reservation stations when we broadcast, not when we dispatch this processor.
So we already have in cycle two both of the reservation stations used.
The first available one will become at cycle 13.
So basically we only cycle 14 we can actually issue this instruction. So
this instruction was waiting to issue, but couldn't because there was no
free reservation station. So let's kind of note this. So
this is just kind of to note that basically we have been delayed in our issue
because of the needing the reservation station. We're using results of R1 and
R3. So we have to wait for the multiplication and ADD before we can execute.
But those are results having broadcast in cycles 13 and five, so in cycle 15,
which is when we can try to execute, we can. If we manage to issue in cycle
four, we will still have to wait until cycle 14 here because of cycle 13 here.
So pretty much, our result will be broadcast in cycle 13.
We will be able to dispatch only in 13, we would be executing in 14. Because we
also needed to wait for a reservation station, we couldn't issue until cycle 14,
so we can only execute in cycle 15. It's a multiplication instruction, so
it's going to try to broadcast the result in cycle 25 and we will be able to
commit it in cycle 46. Now let's look at this attract instruction.
If it's going to try to issue in cycle 15 we have to issue in order.
So although we could have issued this instruction in cycle four as far as,
you know, dependencies are concerned, because we couldn't have
issue this instruction in cycle three, four, five if everything was okay. And
there was a free reservation station at the time here.
But remember, we have to issue instructions in order. Because of that, this will
issue in cycle 15, and we will now grab another reservation station in the ADD,
subtracting. So now what happens is we need to figure out when do we execute?
We need R1 and R5, the R1 comes from this multiplication.
The R5 is already available because none of them are producing it.
The R1 here becomes available after this result is written. So
in cycle 25, we grab the value we need. And then in cycle 26,
we begin executing. It's a subtract. It's going to finish in cycle 27.
And it's going to commit in cycle 47, not because of this, but because of this.
And finally let's look at this ADD here. It's going to issue in cycle 16.
Execution will begin when R4 and R2 are available.
R4 is available in cycle 27, but R2 is available only cycle 42.
So we will dispatch in cycle 42 and begin executing in cycle 43.
We will write our result one cycle after that. And we will commit in cycle 48.
And that concludes our discussion. Now, here you want to make a note, for
example, that the issue has been delayed because of reservation stations. And
for these instructions, for example here, you may want to note that execution
has been delayed because of R2. Just so that if you, on an exam or something,
if you slightly mess this up, if you made these notes at least whoever is
grading this will be able to follow, you know, what went wrong and you know,
what was your real mistake, and what was just a consequence of that mistake.