Hello folks!
So what I want to do in, this video, is to expose you to this very key choice that
device engineers around the world are struggling to make, that is.
Whether they make their FinFETs on a SOI substrate, as shown over here
or they make them on a bulk substrate as shown over here.
And there are pros and cons of,
of taking either of the approach. So, as
I described to you in one of the videos earlier, the way you make FinFET
or the way you define Fins in your SOI substrate is that you have
a fixed fixed thickness of your of your
silicon. And then you you essentially etch that to
describe your Fin.
And so that way you get your Fin height is
determined by your silicon thickness to Start with and
you get these fins which have a very uniform fin
height or in other words, their variation in their fin height is pretty low.
As compared to in
a bulk substrate, the way you define your Fins is you etch
these tall fins. First you fill this
up with an oxide and then you recess that oxide back to expose
your fin. So this introduces a larger variability in
the height of your Fins. So that's one disadvantage
of doing, of making fins using a bulk
substrate. But on the other hand, if
you're looking from economics point of view, bulk
substrate are cheaper as always SOI
substrates are more expensive. So in fact
a lot of initial work on on FinFETs was in fact done on
SOI substrate
so it's shown here is this
very first paper on FinFET of
fully deplted devices from
Hisamoto San in 1990. And he essentially he used this
SOI substrate with this oxide layer and he patterned the silicon
on top into the shape of the Fin. And a lot of initial work in Berkeley
are done on this SOI SOI
substrate, because it's easier to define and control your
.
Also most of the university labs, they don't at
that time didn't used to have any STI process.
on the other hand we saw this Intel announcement where they did use bulk
substrate and they used to define these tall tall Fins.
And then you recessed your oxide back to expose your Fin to
the require, Fin height. So, there are, there are both approaches
which are, you know which were toyed around with and so
coming back to our, pro and, con table because we need to clearly.
make a choice over here so listing out some of
the other arguments One argument one can say is that
you know, when you operate our FinFets, you will generate some heat.
So there would be heat, you know there'd be heat wwhich
will be generated in your FinFet transistor as you keep on operating it.
Especially if you make a microprocessor and operate at very high frequency.
So one of the, advantage of being,
another advantage of being in a
bulk
substrate is that silicon is a decent conductor of heat.
And you can you can easily dissipate your heat into your sub, into your substrate.
On the other hand, if you.
If you are making your FinFET on an SOI substrate, oxide has
a thermal conductivity which is 100 times of the thermal conductivity of silicon.
So the thermal conductivity of oxide
is, you know, two orders of
and two lower than silicon. It becomes pretty hard.
The only way the heat can flow out is
to flow out through these gates, and through these contacts.
But it's harder from a heat prospective over here.
So clearly SOI substrate, one of the problems is heat dissipation.
on the other
hand they, the bulk FinFETS
can be pretty cool about it and dissipate the heaT very neatly.
So lets go back to this pros and cons table over here.
So what I see is, bulk is starting to look good.
It's, it's it's cheaper, it's, cooler. So let me try to balance this out, by,
highlighting, one of the disadvantages that you get, with a bulk technology.
That is you get something which is known as a parasitic BJT.
So let me describe that using this cartoon. So what is this parasitic BJT? So as we discussed earlier. So you have in a FinFET device your gate wrapping around your fin
And it does a pretty good job of controlling the
current in this fin but there's life underneath,
especially if you're making your FinFET on a SOI substrate
So this silicon, Fin, which is, underneath this,
underneath, this, source drain region. So as you can see
over here, there's a silicon fin which is underneath,
and this drain over here can still talk to my source.
using this silicon Fin and if I look at the dopings
over here this is assuming its a nMOS N plus source and drain
I have this P, P silicon fin.
So what I have is essentially a parasitic
BJT and what I have essentially is this BJT.
Which is this
NPN BJT which is in parallel with my silicon FinFET above.
So this is, this is a big problem and has always
been a problem for bulk technology, that you get this parasitic BJT
below your actual. A device and the way people
try to, mitigate the, its effect is by, in this FinFET device,
is by doping this region below the Fin, below your channel.
by a very high doping so what they try to do is, increase the doping over here.
And that helps in
removing this parasitic current or improving your i off so you can see
in this chart over here that this is for a n-FinFET device.
And as people are increasing that doping in this region from 1e16 to.
1e17 all the way up to, 2e18, you see that as you're increasing the doping your
I off is decreasing, and that is typically achieved using this implant in this
region
which is also known as Channel stop implant but
it adds to the process complexity so you need to dope your fin region below your
channel and you really don't want to add that extra process complexity.
This is.
You know, I would say this is an argument, which is against, my my,
bulk
substrate as compared to a
substrate.
So, I essentially have no life underneath my fin.
So, underneath my fin is just my, My oxide
so it has no this issue of parasitic BJT.
Finally, I will end with this one last thing and that is
that goes against my friend SOI MOSFET which so far hasn't been
gone into production.
That is, you have this problem of doing source and drain epitaxy
in a, in a SOI kind of FinFET device.
So, I will explain that using this cartoon over here.
So given these fins on a SOI and bulk substrate.
And when I'm doing a source drain epitaxy, what I do for making this source drain,
and we'll discuss this some more later. If I have want to have more
strain in my source drain, what I do is I etch.
I what I do is I etch this silicon fin in the source drain region
and then I I grow my source drain from this silicon below
and I grow it in a fashion like this. So I grow my SOI
after I do a etchback. And
I can do in this process flow over here because I
have my silicon channel available here so I can regrow my source drain
using my silicon or my bulk as a template. On the other hand
if I come to this, SOI substrate and I etch off
this fin in the source drain region.
There's nothing left below from which I can grow.
So there's there's I can't grow my source-drain
region over here, because there is no template
available for growing this
crystalline
region back. So that's another limitations of SOI.
Flow, so hopefully, you know, I have
highlighted the, some of these pros and cons.
And it's still not clear which is the winner and only that something that only
our friend time can tell us eventually which wins out
.