GDDR5, an abbreviation for double data rate type five synchronous graphics random access
memory, is a modern type of synchronous graphics random access memory with a high bandwidth
interface designed for use in graphics cards, game consoles, and high-performance computation.
Overview Like its predecessor, GDDR4, GDDR5 is based
on DDR3 SDRAM memory which has double the data lines compared to DDR2 SDRAM, but GDDR5
also has 8-bit wide prefetch buffers similar to GDDR4.
GDDR5 SGRAM conforms to the standards which were set out in the GDDR5 specification by
the JEDEC. SGRAM is single-ported. However, it can open two memory pages at once, which
simulates the dual-port nature of other VRAM technologies. It uses an 8n-prefetch architecture
and DDR interface to achieve high performance operation and can be configured to operate
in ×32 mode or ×16 mode which is detected during device initialization. The GDDR5 interface
transfers two 32-bit wide data words per write clock cycle to/from the I/O pins. Corresponding
to the 8n-prefetch, a single write or read access consists of a 256-bit wide two CK clock
cycle data transfer at the internal memory core and eight corresponding 32-bit wide one-half
WCK clock cycle data transfers at the I/O pins.
GDDR5 operates with two different clock types. A differential command clock as a reference
for address and command inputs, and a forwarded differential write clock as a reference for
data reads and writes, that runs at twice the CK frequency. Being more precise, the
GDDR5 SGRAM uses a total of three clocks: two write clocks associated with two bytes
and a single command clock. Taking a GDDR5 with 5 Gbit/s data rate per pin as an example,
the CK clock runs with 1.25 GHz and both WCK clocks at 2.5 GHz. The CK and WCKs are
phase aligned during the initialization and training sequence. This alignment allows read
and write access with minimum latency. A single 32-bit GDDR5 chip has about 67 signal
pins and the rest are power and grounds in the 170 BGA package.
Commercial implementation In 2007, Qimonda, a spin-off of Infineon,
demonstrated and sampled GDDR5, and released a paper about the technologies behind GDDR5.
As of May 10, 2008, Qimonda announced volume production of 512 MB GDDR5 modules rated
at 3.6 Gbps, 4.0 Gbps, and 4.5 Gbps. Hynix Semiconductor introduced the industry's
first 60nm class 1 Gb GDDR5 memory in 2007. It supported a bandwidth of 20 GB/s on a
32-bit bus, which enables memory configurations of 1 GB at 160 GB/s with only 8 circuits
on a 256-bit bus. The following year, in 2008, Hynix bested this technology with its 50nm
class 1 Gb GDDR5 memory. Hynix 40nm class 2 Gb GDDR5 was released in 2010. It operates
at 7 GHz effective clock-speed and processes up to 28 GB/s. 2 Gb GDDR5 memory chips will
enable graphics cards with 2 GB or more of onboard memory with 224 GB/s or higher peak
bandwidth. 4 Gb density GDDR5 modules first starting becoming available in the third quarter
of 2013. Initially released by Hynix, Micron Technology quickly followed up with their
implementation releasing in 2014. Modules from both Micron and Hynix, of both the 2
Gb and 4 Gb densities, range in bit rate up to 7 Gbps.
On June 25, 2008, AMD became the first company to ship products using GDDR5 memory with its
Radeon HD 4870 video card series, incorporating Qimonda's 512 MB memory modules at 3.6 Gbps
bandwidth. On February 20, 2013, it was announced that
the PlayStation 4 will use 4 Gb 512 MB) GDDR5 memory chips for 8 GB of GDDR5 @ 176 Gbps
as combined system and graphics RAM for use with its AMD-powered System on a chip comprising
8 Jaguar cores, 1152 GCN shader processors and AMD TrueAudio.
See also List of device bandwidths
References
External links Introduction To GDDR5 SGRAM(by ELPIDA)
Making Accurate Measurements on GDDR5 Memory Systems
GDDR5 Pinout and Description