So, now let's look at cycle three. In cycle three,
we will try to issue the next instruction which is this multiplication.
We will look at whether we have a unit, yes we do.
Is going to be a multiply instruction. F2 and F4 are LD2 and
the actual value of F4. So here, we will mark the actual value of F4,
this is our second operand as 2.5, because that's what this says.
And then for the first operand, we will mark that we are waiting for LD2.
This is going to make it very easy to determine which things are,
ready to execute, because the instruction should not really have anything here
if it's ready to execute. And this instruction is, not going to be ready yet,
because it's waiting for the second load. And, then we're going to rename F0 so
that it points to, the reservation station, in this case,
ML1, that contains this, instruction. In this third cycle, the first load is
still executing, now the question is, can the second load begin execution?
If we have a pipeline load store unit, then, yes, it would be.
Because in the previous cycle, we have begun this instruction.
It's in the second stage now. So now we can begin the first stage for
this instruction. But let's say we don't have a pipeline load story on it.
That only our add unit is pipelined. In which case,
this load will not be able to dispatch into the execution unit until cycle four
because basically the execution unit will be occupied in cycles two and
three by, the first load. So, we will, [SOUND] kind of mark that in cycle four,
we will be able to, begin execution of this if, everything else is ready. And
nothing is still broadcast in the result. The first load is still,
executing in cycle three. So, now we go to cycle four. In cycle four,
we will try to issue the next instruction, which is this subtract.
It's going to use. And add R unit, so this is, just to mark it as a subtract,
we are going to issue it in this cycle. F2 and F6, or LD2 and LD1, so
this one is actually waiting like this and we also have to,
mark the F8 as renamed. To 81 so this completes the issuing in this cycle.
Now let's see, if we can dispatch something. Well, this is cycle four.
In cycles two and three the first load has been executing now it's ready to
write so basically we can begin execution of this instruction so
it's been dispatched in cycle four now we no longer need this.
Are any of the other instructions ready to execute? Well, not in this cycle so
now we're going to write the result, in LD1. LD1 here,
we kind of note it here that it's going to write the result in cycle four
which is now, so now we're going to write to, the result of this instruction. So
we can mark here that we are writing that result. And, what's going to happen
now is basically is going to broke us with a type of LD1 and the value will be
loaded from memory from this address and that value is going to be put to F6.
So, what we do now is we're going to broke that value and, capture that
value everywhere, where we have LD1 in this table. So, each of these is going to
compare its tag to LD1 and whatever we see in LD1 we're going to get that value.
So. In this case, only this particular instruction is going to latch its value.
So let's say that the value is 7.1. Okay. That completes the result capture.
We still have to put 7.1 in the actual register F6. So
somewhere in F6. We have 7.1 now, because this was pointing to LD1.
LD1 is done now, so, now we can find that value in the register file. And
now we can free this reservation station. So, when you free a reservation
station, what you really do is, you just, turn off the valid bit for the entry,
you don't really have to erase the whole entry. So I'm going to,
erase it just to prepare for the next instruction, but keep in mind that,
in real hardware there is just a single bit that just gets marked zero, and that
is considered to free the reservation station. Now in this cycle, in cycle four,
we have issued an instruction, we have tried to dispatch an instruction, and
we've found that only the load really can be dispatched. And, we have written a,
our result back. Only one result can be written per cycle anyway.
So, that's it for this cycle. So, let's move on to cycle five.